XAPP457 - Powering and Configuring Spartan-3 Generation FPGAs in Compliant PCI Applications (PDF)
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The PCI™ Local Bus Specification defines a number of power and reset requirements. When considered in an FPGA implementation, these create several challenges that must be addressed for long term reliability and broad interoperability. This application note applies to compliant PCI applications using Spartan™-3 Generation FPGAs, and is relevant to other Xilinx FPGA families, as well as related PCI applications.
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1.0 |
170 KB |
06/08/2007 |
XAPP694 - Reading User Data from Configuration PROMs (PDF)
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This application note describes how to retrieve user-defined data from Xilinx configuration PROMs (XC18V00 and Platform Flash devices) after the same PROM has configured the FPGA. The method to add user-defined data to the configuration PROM file is also discussed.
|
1.1.1 |
244 KB |
11/19/2007 |
XAPP250 - Clock and Data Recovery With Coded Data Streams (PDF)
View Document Details
This application note and reference design outline a method to implement clock and data recovery in Virtex®-II devices. Although not limiting the implementation to a specific FPGA family, this reference design focuses on the Virtex-II architecture. With minor modifications, Clock and Data Recovery (CDR) is possible with Virtex-E and Spartan®-IIE devices. A implementation of CDR at 270 Mb/s with 8B/10B coded data is described herein.
|
1.3.2 |
150 KB |
05/02/2007 |
XAPP500 - J Drive: In-System Programming of IEEE Standard 1532 Devices (PDF)
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The J Drive programming engine provides immediate and direct in-system configuration (ISC) support for IEEE Standard 1532 programmable logic devices (PLDs). To configure an in-system device, the programming engine uses the configuration algorithm information from a 1532 Boundary Scan Description Language (BSDL) file to apply configuration data from the 1532 data file through the IEEE Standard 1149.1 test access port (TAP). The J Drive executable, source code, and a programming example are available in a download package from the Xilinx website. The J Drive programming engine can be used for the following Xilinx families: CoolRunner-II CPLDs, XC9500/XL/XV CPLDs, Spartan-3 Generation FPGAs, and Virtex-II (and later) series FPGAs.
|
2.1.2 |
122 KB |
11/12/2007 |
XAPP622 - 644-MHz SDR LVDS Transmitter/Receiver (PDF)
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This application note describes single data rate (SDR) transmitter and receiver interfaces operating at up to 644 MHz, using 17 Low-Voltage Differential Signaling (LVDS) pairs (one clock and 16 data channels). The design can be implemented in both Virtex-II™ and Virtex-II Pro™ FPGAs. The accompanying reference design files include an example implementation targeting a Virtex-II XC2V3000FF1152 -5 speed grade device.
|
1.7 |
158 KB |
04/27/2004 |
XAPP1002 - Using ChipScope Pro to Debug Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE (PDF)
View Document Details
This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI
Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.
|
1.0 |
1.27 MB |
10/22/2007 |
XAPP1022 - Using MET with PIO Example Design for PCI Express Endpoint Cores (PDF)
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This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with the Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE for PCI Express® Xilinx solutions.
|
1.0 |
1.19 MB |
09/19/2007 |
XAPP868 - Clock Data Recovery Design Techniques for E1/T1 Based on Direct Digital Synthesis (PDF)
View Document Details
This document details the design aspects of digital PLLs implemented in Virtex® and Spartan® FPGAs for telecommunications applications. PLL performance and loop stability are evaluated.
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1.0 |
287 KB |
01/29/2008 |
XAPP802 - Memory Interface Application Notes Overview (PDF)
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This document provides an overview of all Xilinx memory interface application notes that support Virtex™ Series FPGAs. In addition, some key features of the prevalent memory technologies are also provided. For each application note, the data capture technique, clocking scheme, FPGA resources used, and supported memory technology are described briefly. Was this document helpful? Yes | No
|
1.9 |
301 KB |
03/26/2007 |
XAPP800 - Configuring Xilinx FPGAs with SPI Flash Memories Using CoolRunner-II CPLDs (PDF)
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This application note describes a method to configure Xilinx FPGAs, such as Spartan®-IIE and Spartan-3 FPGAs, using inexpensive small Serial Peripheral Interface (SPI) flash memories.
|
1.1.1 |
548 KB |
04/24/2008 |
XAPP780 - FPGA IFF Copy Protection Using Dallas Semiconductor/Maxim DS2432 Secure EEPROMs (PDF)
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This application note describes a cost-optimized copy protection scheme that helps protect an FPGA against cloning. The design leverages an external secure serial EEPROM. The included reference design uses an optimized PicoBlaze™ 8-bit microcontroller. This application note provides a hardware design with associated PicoBlaze software code. The code loads a secret key into the secure EEPROM and authenticates the user system with the secure EEPROM.
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1.0 |
114 KB |
08/17/2005 |
XAPP774 - Connecting Xilinx FPGAs to Texas Instruments ADS527x Series ADCs (PDF)
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This application note describes how to connect a high-speed Texas Instruments (TI) ADS5273 analog-to-digital converter (ADC) with serialized LVDS output to a Virtex™-II or Virtex™-II Pro FPGA. Lower speed ADC devices from this family can be connected to Spartan™-3 FPGAs.
|
1.2 |
239 KB |
02/23/2006 |
XAPP753 - Interfacing Xilinx FPGAs to TI DSP Platforms Using the EMIF (PDF)
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This application note shows the connection of Xilinx® FPGAs to a Texas Instruments™ S320C6000 series Digital Signal Processor (DSP) using the available External Memory Interface (EMIF).
|
2.0.1 |
1.54 MB |
01/29/2007 |
XAPP569 - Digital Up and Down Converters for the CDMA2000 and UMTS Base Stations (PDF)
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This application note describes a reference design of multi-channel digital up converters(DUCs) and digital down converters (DDCs) for CDMA2000 and UMTS base stations. The
provided DSP algorithms meet base station specifications using digital-to-analog conversion rates of 61.44 MHz. Four-channel implementations are described that efficiently map the DSP algorithms into the resources of the Spartan™-3 family of FPGAs.
|
1.0.1 |
717 KB |
08/10/2006 |
XAPP562 - Configurable LocalLink CRC Reference Design (PDF)
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The Cyclic Redundancy Check (CRC) is a powerful technique to obtain data reliability. This application note discusses the implementation of Configurable CRC Modules with LocalLink interfaces. The user can tailor the features of these modules to suit the protocol or application that is implemented in their system. The user-specified options for each of the configurable features are input parameters to the VHDL code for the modules.
|
1.1.1 |
218 KB |
04/20/2007 |
XAPP551 - Viterbi Decoder Block Decoding - Trellis Termination and Tail Biting (PDF)
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This application note explains how to use the Xilinx Viterbi Decoder LogiCORE™ module (version 5.0 or later) to implement both trellis termination and tail biting. Was this document helpful? Yes | No
|
1.0 |
139 KB |
02/14/2005 |
XAPP529 - Connecting Customized IP to the MicroBlaze Soft Processor Using the Fast Simplex Link(FSL) (PDF)
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MicroBlaze™ has the ability to use its dedicated FSL bus interface to integrate a customized IP core into a MicroBlaze soft processor-based system. This document describes possible methods to include customized IP cores into an SCP-based design.
|
1.3 |
177 KB |
05/12/2004 |
XAPP501 - Configuration Quick Start Guidelines (PDF)
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This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families. Was this document helpful? Yes | No
|
1.5 |
249 KB |
10/02/2007 |
XAPP491 - Inverting LVDS Signals for Efficient PCB Layout in Spartan-3 Generation FPGAs (PDF)
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Differential signals, such as LVDS or LVPECL, can be difficult to route on simple, four-layer or six-layer PCBs without excessive use of vias. This application note shows how Spartan™-3 Generation FPGAs, with just the inclusion of an inverter in the datapath, can avoid excessive use of vias and fix accidental PCB trace swapping without requiring a PCB respin.
|
1.0 |
288 KB |
10/04/2006 |
XAPP482 - MicroBlaze Platform Flash/PROM Boot Loader and User Data Storage (PDF)
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XAPP482 describes a working MicroBlaze™ system that stores software code, user data, and configuration data in non-volatile Platform Flash PROMs, simplifying system design and reducing cost. It provides a portable hardware design, software design, and additional script utilities to be used during the implementation flow.
|
2.0 |
199 KB |
06/27/2005 |
XAPP476 - Using BSDL Files for Spartan-3 Generation FPGAs (PDF)
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For the latest version of this application note, see the BSDL chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide. Was this document helpful? Yes | No
|
1.1 |
65 KB |
06/19/2005 |
XAPP475 - Using IBIS Models for Spartan-3 FPGAs (PDF)
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For the latest version of this application note, see the IBIS chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide. Was this document helpful? Yes | No
|
1.0 |
40 KB |
06/21/2003 |
XAPP466 - Using Dedicated Multiplexers in Spartan-3 Generation FPGAs (PDF)
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For the latest version of this application note, see the Multiplexers chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.
|
1.1 |
142 KB |
05/20/2005 |
XAPP465 - Using Look-Up Tables as Shift Registers (SRL16) in Spartan-3 Generation FPGAs (PDF)
View Document Details
For the latest version of this application note, see the SRL16 chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.
|
1.1 |
219 KB |
05/20/2005 |
XAPP464 - Using Look-Up Tables as Distributed RAM in Spartan-3 Generation FPGAs (PDF)
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For the latest version of this application note, see the Distributed RAM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.
|
2.0 |
118 KB |
03/01/2005 |
XAPP463 - Using Block RAM in Spartan-3 Generation FPGAs (PDF)
View Document Details
For the latest version of this application note, see the Block RAM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.
|
2.0 |
415 KB |
03/01/2005 |
XAPP462 - Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs (PDF)
View Document Details
For the latest version of this application note, see the DCM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.
|
1.1 |
796 KB |
01/05/2006 |
XAPP456 - Custom PCI Timing Budgets for Spartan-3 Generation FPGAs (PDF)
View Document Details
The PCI specification defines two I/O timing budgets for use with 33 MHz and 66 MHz operation. In embedded designs, custom timing budgets enable the following:
• Reduce total system cost by using less expensive devices
• Achieve higher data transfer rates than allowed by specification
• Add more loads to the bus to accommodate additional devices and connectors
• Increase the physical length of the bus to accommodate novel bus topologies
The information presented in this application note is applicable to any embedded PCI implementation using Xilinx FPGA devices. Was this document helpful? Yes | No
|
1.0 |
238 KB |
03/13/2007 |
XAPP454 - DDR2 SDRAM Interface for Spartan-3 Generation FPGAs (PDF)
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This application note describes a DDR2 SDRAM interface implementation in a Spartan®-3 generation FPGA, interfacing with a Micron DDR2 SDRAM device. This document provides a brief overview of the DDR2 SDRAM device features, followed by a detailed explanation of the DDR2 SDRAM interface implementation. Was this document helpful? Yes | No
|
2.1 |
328 KB |
01/20/2009 |
XAPP195 - Implementing Barrel Shifters Using Multipliers (PDF)
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The Virtex™-II family of platform FPGAs has multipliers embedded into the FPGA fabric. These multipliers support several different multiplication modes of operation and can also function as barrel shifters.
|
1.1 |
52 KB |
08/17/2004 |
XAPP229 - Wider Block Memories (PDF)
View Document Details
This application note describes how memories wider than 36 bits can be efficiently implemented in the Virtex™-II and Spartan™-3 architectures. The clock-doubling method used
is similar to the method described for quad-port memories in XAPP228. The resulting memories are used in either dual-port or single-port mode.
|
1.1.1 |
75 KB |
04/19/2007 |
XAPP225 - Data to Clock Phase Alignment (PDF)
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When designing digital systems, there is often a requirement to synchronize incoming data and clock signals with an internal system clock, i.e., the internal and external clock are at exactly the same frequency, but due to variable backplane, board, or application-specific standard product (ASSP) delays, the phase relationship is not known. The circuit described in this application note addresses this issue for both single traces and data buses up to 210 MHz in a Virtex®-II -5 device. The speed limitation is imposed by the maximum frequency that can be accepted by the Digital Clock Manager (DCM), in a mode where it is capable of providing both a new clock and a new clock shifted by 90 degrees.
|
1.3 |
153 KB |
02/18/2008 |
XAPP224 - Data Recovery (PDF)
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Data recovery is a mechanism that allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts this information from the data stream concerned, but sometimes the receiver’s clock is used for data transmission. The circuit described in this application note provides a partial solution at data rates up to 160 Mb/s in a Virtex™-E -7 device, a Spartan™-IIE -6 device, or a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro™ -6 device. The solution is partial in the sense that no clock is actually recovered, but the data arriving is fully extracted. The speed is limited by the maximum frequency that can be accepted by the Delay Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock, and another clock shifted by 90 degrees.
|
2.5 |
206 KB |
07/11/2005 |
XAPP211 - PN Generators Using the SRL Macro (PDF)
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Pseudo-random Noise (PN) generators are at the heart of every spread spectrum system. Many PN generators are required within Code Division Multiple Access (CDMA) base stations. PN generators are used to implement synchronization and uniquely code individual user signals across the transmission interface. PN generators are based upon Linear Feedback Shift Registers (LFSRs). Every Look-Up-Table (LUT) in a Virtex™ series or Virtex™-II series device can be configured as a 16-bit shift register (SRL16 macro). Hence, Virtex devices implement efficient LFSRs and deliver a significant reduction in resource utilization when compared with alternative flip-flop-only PLD structures.
|
1.2 |
111 KB |
06/14/2004 |
XAPP201 - An Overview of Multiple CAM Designs in Virtex Devices (PDF)
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Flexible CAMs (Content Addressable Memory) are implemented in Virtex™ devices by taking advantage of the reprogrammability of the basic LUT as a Shift Register or a SelectRAM™ memory and the fast carry logic chain. Although CAMs are also feasible in Spartan™ and XC4000X™ devices, this application note concentrates on Virtex devices. Was this document helpful? Yes | No
|
1.1 |
47 KB |
09/23/1999 |
XAPP453 - The 3.3V Configuration of Spartan-3 FPGAs (PDF)
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This application note describes an approach to the 3.3V configuration of Spartan®-3 FPGAs. It provides a set of proven connection diagrams for each configuration mode. The same approach can be applied to the Spartan-3E family. Was this document helpful? Yes | No
|
1.1.1 |
215 KB |
06/23/2008 |
XAPP452 - Spartan-3 FPGA Family Advanced Configuration Architecture (PDF)
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This application note provides a detailed description of the Spartan®-3 FPGA family configuration architecture. It explains the composition of the bitstream file and how this bitstream is interpreted by the configuration logic to program the part. Was this document helpful? Yes | No
|
1.1 |
388 KB |
06/26/2008 |
XAPP441 - Remote FPGA Reconfiguration Using MicroBlaze or PowerPC (PDF)
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This application note describes techniques for remote reconfiguration of FPGAs through an Ethernet port.
|
1.1 |
480 KB |
09/09/2006 |
XAPP427 - Implementation and Solder Reflow Guidelines for Pb-Free Packages (PDF)
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This application note contains guidelines on reflow soldering, inspection, and rework process for Pb-free packages. Was this document helpful? Yes | No
|
2.4 |
119 KB |
02/12/2009 |
XAPP259 - System Interface Timing Parameters (PDF)
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This application note defines timing parameters required for the timing analysis of source synchronous and system synchronous applications. The parameters discussed in this
application note are listed in Module 3 of the Virtex™-II and Virtex-II Pro™ data sheets. This application note explains the DCM clock phase accuracy parameters, system-synchronous pin-to-pin setup/hold with DCM parameters (TPSDCM and TPHDCM), and all source-synchronous parameters. Memory interfaces and the XGMII interface analyses are provided as examples Was this document helpful? Yes | No
|
1.0 |
352 KB |
04/28/2003 |
XAPP251 - Hot-Swapping Virtex-II, Virtex-II Pro, Virtex-4, and Virtex-5 Devices (PDF)
View Document Details
Hot-swapping or hot insertion describes a potentially dangerous method of inserting an unpowered board into a power-on (hot) running system. There are several concerns: the insertion must not cause physical harm or permanent damage to the system or the inserted board, and the insertion must not cause data corruption or any transient system upsets. This application note describes the physical aspects of hot-inserting a Virtex™-II based card into a system or system backplane, using sequenced connectors, where VCC and GND mate well before any signal pins can mate. The dangers of using normal non-sequenced connectors are described in Hot Plug-In. Not addressed in this application note are system issues including detecting the presence or absence of a card, or how the card is accepted in the system. Was this document helpful? Yes | No
|
1.3.1 |
125 KB |
05/14/2007 |
XAPP942 - Reference System: OPB Ethernet MAC (PDF)
|
1.0 |
188 KB |
10/20/2006 |
XAPP863 - Using Digitally Controlled Impedance: Signal Integrity vs Power Dissipation Considerations (PDF)
View Document Details
On-die termination (ODT) promises higher signaling rates for printed circuit board (PCB) inter-chip interfaces through improved signal integrity. However, when using ODT, there is sometimes an associated power penalty. This application note explains the reason for the power penalty and suggests a simulation technique for comparing the signal integrity and power dissipation of internally and externally terminated versions of an interface.
|
1.0 |
1011 KB |
06/01/2007 |
XAPP936 - Continuously Variable Fractional Rate Decimator (PDF)
View Document Details
This application note focuses on the baseband demodulation of Quadrature Amplitude Modulation (QAM) signals and, more specifically, on the use of a fractional rate decimator block. This application note also reviews polyphase decimating filter architectures and discusses the fractional rate decimator, its Xilinx System Generator 8.1i implementation, and its results.
|
1.1 |
422 KB |
03/05/2007 |
XAPP933 - Two-Dimensional Linear Filtering (PDF)
View Document Details
This application note provides a Xilinx FPGA solution to two-dimensional filtering with a parameterized VHDL reference design.
|
1.1 |
233 KB |
10/23/2007 |
XAPP932 Chroma Resampler (PDF)
View Document Details
This application note describes the implementation of six circuits necessary to perform commonly used conversions between various chroma formats.
|
1.0 |
394 KB |
05/09/2006 |
XAPP726 - Benefits of FPGAs in Wireless Base Station Baseband Processing Applications (PDF)
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Provides an overview of the baseband processing of a typical W-CDMA base station, along with the associated implementation challenges faced by W-CDMA equipment manufacturers, including the silicon cost, flexibility, and scalability trade-offs. Was this document helpful? Yes | No
|
1.0 |
250 KB |
07/25/2005 |
XAPP931 - Color-Space Converter: YCrCb to RGB (PDF)
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This application note describes the implementation of a YCrCb color space to an RGB Color space conversion circuit necessary in many video designs.
|
1.1 |
335 KB |
10/13/2006 |
XAPP930 - Color-Space Converter: RGB to YCrCb (PDF)
View Document Details
This application note describes the implementation of an RGB color space to a YCbCr color space conversion circuit necessary in many video designs.
|
1.0.1 |
326 KB |
08/27/2007 |
XAPP923 - Reference Design: MCH OPB EMC with OPB Central DMA (PDF)
View Document Details
This application note demonstrates the use of the Multi CHannel (MCH) On Chip Peripheral Bus (OPB) External Memory Controller (EMC) in a MicroBlaze processor system.
|
1.2 |
736 KB |
06/05/2007 |
XAPP918 - Incremental Design Reuse with Partitions (PDF)
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This application note discusses the use of Partitions in the Incremental Design Flow. It is recommended that module instances with high logic density, timing critical paths, or timing critical module instances be designated Partitions. Was this document helpful? Yes | No
|
1.0 |
1.03 MB |
06/07/2007 |
XAPP909 - Reference System: MCH OPB SDRAM with OPB Central DMA (PDF)
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This application note demonstrates the use of the Multi-Channel OPB Synchronous DRAM controller in a MicroBlaze™ processor system.
|
1.3 |
798 KB |
06/05/2007 |
XAPP808 - FPGA Motor Control Reference Design (PDF)
|
1.0 |
604 KB |
09/16/2005 |
XAPP806 - Determining the Optimal DCM Phase Shift for the DDR Feedback Clock (PDF)
View Document Details
This application note describes how to build a system that can be used for determining the optimal phase shift for a DDR memory feedback clock. In this system, the DDR memory is controlled by a controller that attaches to either the OPB or PLB and is used in an embedded microprocessor application. This reference system also uses a DCM that is configured so that the phase of its output clock can be changed while the system is running and a GPIO core that controls that phase shift. The GPIO output is controlled by a software application that can be run on a PPC or MicroBlaze™ microprocessor
|
1.2 |
411 KB |
06/05/2007 |
XAPP953 - Two-Dimensional Rank Order Filter (PDF)
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This application note describes the implementation of a two-dimensional Rank Order filter. The reference design includes the RTL VHDL implementation of an efficient sorting algorithm.
|
1.1 |
431 KB |
09/21/2006 |
XAPP948 - Hardware Acceleration of 3GPP Turbo Encoder/Decoder BER Measurement Using System Generator (PDF)
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1.0 |
808 KB |
12/05/2006 |
XAPP696 - Interfacing LVPECL 3.3V Drivers with Xilinx 2.5V Differential Receivers (PDF)
View Document Details
This application note describes how to interface 3.3V differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) drivers with Xilinx® 2.5V differential receivers, including Virtex®-II Pro, Virtex-II Pro X, Virtex-4, Virtex-5, Spartan®-3E, and Spartan-3 FPGA 2.5V LVPECL and Low Voltage Differential Signaling (LVDS). Several interface modifications are presented with supporting IBIS simulation results. Was this document helpful? Yes | No
|
1.3 |
324 KB |
05/01/2008 |
XAPP693 - A CPLD-Based Configuration and Revision Manager for Xilinx Platform Flash PROMs and FPGAs (PDF)
View Document Details
This application note illustrates the use of a Xilinx CoolRunner-II™ CPLD to monitor configuration data between a Xilinx Platform Flash Configuration PROM and a Xilinx Spartan™ or Virtex™ family FPGA. The intent is to ensure reliable configuration of the FPGA while providing revision control for one or more configuration files stored in the PROM.
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1.1 |
100 KB |
01/19/2005 |
XAPP690 - Using Block SelectRAM Memories as Serializers or Deserializers (PDF)
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This application note describes how block memories efficiently can implement a serializer or a deserializer function or both with or without pattern-matching capabilities in the Virtex™-II, Virtex-II Pro™, and Spartan™-3 architectures.
|
1.0 |
97 KB |
10/06/2003 |
XAPP689 - Managing Ground Bounce in Large FPGAs (PDF)
View Document Details
Ground bounce must be controlled to ensure proper operation of high performance FPGA devices. Particular attention must be applied to minimizing board-level inductance during PCB layout. This document describes calculations that help to ensure that a design meets input undershoot and logic-low voltage requirements for devices receiving signals from an FPGA.
|
1.2 |
90 KB |
10/30/2007 |
XAPP659 - Virtex-II Pro / Virtex-II Pro X 3.3V I/O Design Guidelines (PDF)
View Document Details
This application note describes how to interface 3.3V I/O in a Virtex™-II Pro system design. Topics include using the LVDCI_33 I/O standard to interface to LVCMOS or LVTTL external interfaces, Peripheral Component Interface (PCI) bus interface solutions, device configuration, and other board-level design techniques. Was this document helpful? Yes | No
|
1.7 |
419 KB |
04/24/2007 |
XAPP646 - Connecting Virtex-II Devices to a 3.3V/5V PCI Bus (PDF)
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This application note describes how to connect Virtex™-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan™-3, and Spartan-3E devices to 3.3V or 5V PCI buses. The design responds to customer demand for a general solution for applications with a Virtex-II device and a 5V PCI bus, as well as for applications with a Virtex-II Pro, Virtex-4, Virtex-5, Spartan-3, or Spartan-3E device and a 3.3V or 5V PCI bus. Was this document helpful? Yes | No
|
1.2.2 |
65 KB |
04/23/2007 |
XAPP636 - Optimal Pipelining of the I/O Ports of the Virtex-II Multiplier (PDF)
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This application note describes a high-speed, optimized implementation of a Virtex-II™ pipelined multiplier primitive (MULT18X18 and MULT18X18S) implemented in VHDL and Verilog.
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1.4 |
128 KB |
06/24/2004 |
XAPP623 - Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors (PDF)
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This application note covers the principles of power distribution systems and bypass or decoupling capacitors. A step-by-step process is described where a power distribution system can be designed and verified. The final section discusses additional sources of power supply noise and provides resolutions.
|
2.1 |
437 KB |
02/28/2005 |
XAPP1038 - Reference System: PLBv46 PCI Using the Avnet Spartan-3 FPGA Evaluation Board (PDF)
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This application note describes how to build a reference system for the Processor Local Bus Peripheral Component Interconnect (PLBv46 PCI) Core using the MicroBlaze™ processor-based embedded system in the Avnet Spartan™-3 Evaluation Board.
|
1.0 |
3.06 MB |
02/08/2008 |
XAPP459 - Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Generation FPGAs (PDF)
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This application note describes solutions to receive large-swing signals by design. In one solution (and in the general case of severe positive and/or negative overshoot), parasitic leakage current between User I/O in differential pin pairs may occur, even though the User I/O pins are configured with single-ended I/O standards. This application note addresses the parasitic leakage current behavior. Was this document helpful? Yes | No
|
1.0 |
457 KB |
04/18/2008 |
XAPP058 - Xilinx In-System Programming Using an Embedded Microcontroller (PDF)
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The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.
|
4.1 |
641 KB |
03/06/2009 |
XAPP258 - FIFOs Using Virtex-II Block RAM (PDF)
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The Virtex®-II FPGA series provides dedicated on-chip blocks of 18 Kbit True Dual-Port synchronous RAM for use in FIFO applications. This application note describes a way to create a common-clock (synchronous) version and an independent-clock (asynchronous) version of a 511 to 36 FIFO, with the depth and width being adjustable within the Verilog or VHDL code.
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1.4 |
70 KB |
01/07/2005 |
XAPP634 - Analog Devices TigerSHARC Link (PDF)
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This application note describes a full-featured transmitter/receiver macro that can communicate with Spartan® and Virtex® FPGA families via the Analog Devices ADSP-TS101S TigerSHARC™ link-port function.
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1.2 |
67 KB |
10/26/2004 |
XAPP228 - Quad-Port Memories in Virtex Devices (PDF)
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This application note describes how the existing dual-port block memories in the Spartan®-II and Virtex® families can be used as Quad-Port memories. This essentially involves a data access time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the block memory in terms of bits per second will remain the same.
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1.0 |
61 KB |
09/24/2002 |
XAPP260 - Using Virtex-II Block RAM for High Performance Read/Write CAMs (PDF)
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Content Addressable Memory (CAM) offers increased data search speed. In various applications based on CAM, there are differing requirements for data organizations and read/write performance. The innovative design described in this application note is suited for small embedded CAMs with high-speed match and write requirements. The reference design is built using the true dual-port block SelectRAM™+ feature for the Virtex®-II series, including the Virtex-II Pro devices.
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1.1 |
127 KB |
02/27/2002 |
XAPP291 - Self-Addressing FIFO (PDF)
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The block memories in the Virtex®-II architecture are capable of supporting data bus widths of up to 36-bits. A self-addressing FIFO reference design uses these block memories to store both data and address information in a single memory location. This application note describes FIFO designs where no external counters are required. Only flag and status information logic is used. The resulting FIFOs are not fast (around 150 MHz). Their advantage is in using only one clock load. In addition, the status mechanism is very simple making FIFOs are more suitable for data throttling in continuous data systems instead of the full or empty detection required in frame-based data systems.
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1.3 |
101 KB |
06/03/2005 |
XAPP467 - Using Embedded Multipliers in Spartan-3 FPGAs (PDF)
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Describes the multipliers in the original Spartan®-3 FPGA architecture. For the Spartan-3E/-3A FPGA families, see the Multipliers chapter in User Guide UG331, Spartan-3 Generation FPGA User Guide.
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1.1 |
183 KB |
05/13/2003 |
XAPP503 - SVF and XSVF File Formats for Xilinx Devices (PDF)
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This application note provides users with a general understanding of the SVF and XSVF file formats as they apply to Xilinx® devices. Some familiarity with IEEE STD 1149.1 (JTAG) is assumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format (XSVF) files in embedded programming applications, refer to Xilinx Application Note XAPP058. Was this document helpful? Yes | No
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2.1 |
372 KB |
08/17/2009 |
XAPP502 - Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode (PDF)
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In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.
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1.6.1 |
356 KB |
08/24/2009 |