XAPP806 - Determining the Optimal DCM Phase Shift for the DDR Feedback Clock (PDF)
View Document Details
This application note describes how to build a system that can be used for determining the optimal phase shift for a DDR memory feedback clock. In this system, the DDR memory is controlled by a controller that attaches to either the OPB or PLB and is used in an embedded microprocessor application. This reference system also uses a DCM that is configured so that the phase of its output clock can be changed while the system is running and a GPIO core that controls that phase shift. The GPIO output is controlled by a software application that can be run on a PPC or MicroBlaze™ microprocessor
|
1.2 |
411 KB |
06/05/2007 |
XAPP780 - FPGA IFF Copy Protection Using Dallas Semiconductor/Maxim DS2432 Secure EEPROMs (PDF)
View Document Details
This application note describes a cost-optimized copy protection scheme that helps protect an FPGA against cloning. The design leverages an external secure serial EEPROM. The included reference design uses an optimized PicoBlaze™ 8-bit microcontroller. This application note provides a hardware design with associated PicoBlaze software code. The code loads a secret key into the secure EEPROM and authenticates the user system with the secure EEPROM.
|
1.0 |
114 KB |
08/17/2005 |
XAPP501 - Configuration Quick Start Guidelines (PDF)
View Document Details
This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families. Was this document helpful? Yes | No
|
1.5 |
249 KB |
10/02/2007 |
XAPP491 - Inverting LVDS Signals for Efficient PCB Layout in Spartan-3 Generation FPGAs (PDF)
View Document Details
Differential signals, such as LVDS or LVPECL, can be difficult to route on simple, four-layer or six-layer PCBs without excessive use of vias. This application note shows how Spartan™-3 Generation FPGAs, with just the inclusion of an inverter in the datapath, can avoid excessive use of vias and fix accidental PCB trace swapping without requiring a PCB respin.
|
1.0 |
288 KB |
10/04/2006 |
XAPP486 - 7:1 Serialization in Spartan-3E FPGAs at Speeds Up to 666 Mbps (PDF)
View Document Details
This application note targets Spartan™-3E devices in applications that require 4-bit or 5-bit transmit data bus widths and operate at rates up to 666 Mbps per line with a forwarded clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.
|
1.0 |
700 KB |
03/09/2007 |
XAPP485 - 1:7 Deserialization in Spartan-3E/3A FPGAs at Speeds Up to 666 Mbps (PDF)
View Document Details
This application note targets Spartan®-3E/3A devices in applications that require 4-bit or 5-bit receive data bus widths and operate at rates up to 666 Mbps per line with a clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.
|
1.2 |
506 KB |
05/27/2008 |
XAPP482 - MicroBlaze Platform Flash/PROM Boot Loader and User Data Storage (PDF)
View Document Details
XAPP482 describes a working MicroBlaze™ system that stores software code, user data, and configuration data in non-volatile Platform Flash PROMs, simplifying system design and reducing cost. It provides a portable hardware design, software design, and additional script utilities to be used during the implementation flow.
|
2.0 |
199 KB |
06/27/2005 |
XAPP476 - Using BSDL Files for Spartan-3 Generation FPGAs (PDF)
View Document Details
For the latest version of this application note, see the BSDL chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide. Was this document helpful? Yes | No
|
1.1 |
65 KB |
06/19/2005 |
XAPP466 - Using Dedicated Multiplexers in Spartan-3 Generation FPGAs (PDF)
View Document Details
For the latest version of this application note, see the Multiplexers chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.
|
1.1 |
142 KB |
05/20/2005 |
XAPP465 - Using Look-Up Tables as Shift Registers (SRL16) in Spartan-3 Generation FPGAs (PDF)
View Document Details
For the latest version of this application note, see the SRL16 chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.
|
1.1 |
219 KB |
05/20/2005 |
XAPP464 - Using Look-Up Tables as Distributed RAM in Spartan-3 Generation FPGAs (PDF)
View Document Details
For the latest version of this application note, see the Distributed RAM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.
|
2.0 |
118 KB |
03/01/2005 |
XAPP463 - Using Block RAM in Spartan-3 Generation FPGAs (PDF)
View Document Details
For the latest version of this application note, see the Block RAM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.
|
2.0 |
415 KB |
03/01/2005 |
XAPP462 - Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs (PDF)
View Document Details
For the latest version of this application note, see the DCM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.
|
1.1 |
796 KB |
01/05/2006 |
XAPP456 - Custom PCI Timing Budgets for Spartan-3 Generation FPGAs (PDF)
View Document Details
The PCI specification defines two I/O timing budgets for use with 33 MHz and 66 MHz operation. In embedded designs, custom timing budgets enable the following:
• Reduce total system cost by using less expensive devices
• Achieve higher data transfer rates than allowed by specification
• Add more loads to the bus to accommodate additional devices and connectors
• Increase the physical length of the bus to accommodate novel bus topologies
The information presented in this application note is applicable to any embedded PCI implementation using Xilinx FPGA devices. Was this document helpful? Yes | No
|
1.0 |
238 KB |
03/13/2007 |
XAPP229 - Wider Block Memories (PDF)
View Document Details
This application note describes how memories wider than 36 bits can be efficiently implemented in the Virtex™-II and Spartan™-3 architectures. The clock-doubling method used
is similar to the method described for quad-port memories in XAPP228. The resulting memories are used in either dual-port or single-port mode.
|
1.1.1 |
75 KB |
04/19/2007 |
XAPP225 - Data to Clock Phase Alignment (PDF)
View Document Details
When designing digital systems, there is often a requirement to synchronize incoming data and clock signals with an internal system clock, i.e., the internal and external clock are at exactly the same frequency, but due to variable backplane, board, or application-specific standard product (ASSP) delays, the phase relationship is not known. The circuit described in this application note addresses this issue for both single traces and data buses up to 210 MHz in a Virtex®-II -5 device. The speed limitation is imposed by the maximum frequency that can be accepted by the Digital Clock Manager (DCM), in a mode where it is capable of providing both a new clock and a new clock shifted by 90 degrees.
|
1.3 |
153 KB |
02/18/2008 |
XAPP224 - Data Recovery (PDF)
View Document Details
Data recovery is a mechanism that allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts this information from the data stream concerned, but sometimes the receiver’s clock is used for data transmission. The circuit described in this application note provides a partial solution at data rates up to 160 Mb/s in a Virtex™-E -7 device, a Spartan™-IIE -6 device, or a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro™ -6 device. The solution is partial in the sense that no clock is actually recovered, but the data arriving is fully extracted. The speed is limited by the maximum frequency that can be accepted by the Delay Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock, and another clock shifted by 90 degrees.
|
2.5 |
206 KB |
07/11/2005 |
XAPP453 - The 3.3V Configuration of Spartan-3 FPGAs (PDF)
View Document Details
This application note describes an approach to the 3.3V configuration of Spartan®-3 FPGAs. It provides a set of proven connection diagrams for each configuration mode. The same approach can be applied to the Spartan-3E family. Was this document helpful? Yes | No
|
1.1.1 |
215 KB |
06/23/2008 |
XAPP489 - Four- and Six-Layer, High-Speed PCB Design for the Spartan-3E FT256 BGA Package (PDF)
View Document Details
This application note addresses low-cost, four- to six-layer, high-volume printed circuit board (PCB) layout for a Spartan™-3E FPGA in the FT256 1 mm BGA package. Intended for design engineers, managers, and PCB layout staff, who are already familiar with SI related design issues. The general guidelines can be used to optimize board layout for other devices and packages.
|
1.0 |
882 KB |
10/31/2006 |
XAPP441 - Remote FPGA Reconfiguration Using MicroBlaze or PowerPC (PDF)
View Document Details
This application note describes techniques for remote reconfiguration of FPGAs through an Ethernet port.
|
1.1 |
480 KB |
09/09/2006 |
XAPP427 - Implementation and Solder Reflow Guidelines for Pb-Free Packages (PDF)
View Document Details
This application note contains guidelines on reflow soldering, inspection, and rework process for Pb-free packages. Was this document helpful? Yes | No
|
2.4 |
119 KB |
02/12/2009 |
XAPP251 - Hot-Swapping Virtex-II, Virtex-II Pro, Virtex-4, and Virtex-5 Devices (PDF)
View Document Details
Hot-swapping or hot insertion describes a potentially dangerous method of inserting an unpowered board into a power-on (hot) running system. There are several concerns: the insertion must not cause physical harm or permanent damage to the system or the inserted board, and the insertion must not cause data corruption or any transient system upsets. This application note describes the physical aspects of hot-inserting a Virtex™-II based card into a system or system backplane, using sequenced connectors, where VCC and GND mate well before any signal pins can mate. The dangers of using normal non-sequenced connectors are described in Hot Plug-In. Not addressed in this application note are system issues including detecting the presence or absence of a card, or how the card is accepted in the system. Was this document helpful? Yes | No
|
1.3.1 |
125 KB |
05/14/2007 |
XAPP963 - Using and Creating Flash Files for the MicroBlaze Development Kit - Spartan-3E Edition (PDF)
|
1.1 |
640 KB |
11/28/2007 |
XAPP933 - Two-Dimensional Linear Filtering (PDF)
View Document Details
This application note provides a Xilinx FPGA solution to two-dimensional filtering with a parameterized VHDL reference design.
|
1.1 |
233 KB |
10/23/2007 |
XAPP932 Chroma Resampler (PDF)
View Document Details
This application note describes the implementation of six circuits necessary to perform commonly used conversions between various chroma formats.
|
1.0 |
394 KB |
05/09/2006 |
XAPP931 - Color-Space Converter: YCrCb to RGB (PDF)
View Document Details
This application note describes the implementation of a YCrCb color space to an RGB Color space conversion circuit necessary in many video designs.
|
1.1 |
335 KB |
10/13/2006 |
XAPP930 - Color-Space Converter: RGB to YCrCb (PDF)
View Document Details
This application note describes the implementation of an RGB color space to a YCbCr color space conversion circuit necessary in many video designs.
|
1.0.1 |
326 KB |
08/27/2007 |
XAPP928 - Digital Display Panel Reference Design (PDF)
View Document Details
This is a reference design for the Spartan™-3E Display Development Kit to assist in developing display panel products. The display solution FPGA design consists of a Video Input interface, Color Temperature Correction, Precise Gamma Correction, Image Dithering Engine, and an output interface.
|
1.1 |
580 KB |
04/19/2007 |
XAPP918 - Incremental Design Reuse with Partitions (PDF)
View Document Details
This application note discusses the use of Partitions in the Incremental Design Flow. It is recommended that module instances with high logic density, timing critical paths, or timing critical module instances be designated Partitions. Was this document helpful? Yes | No
|
1.0 |
1.03 MB |
06/07/2007 |
XAPP953 - Two-Dimensional Rank Order Filter (PDF)
View Document Details
This application note describes the implementation of a two-dimensional Rank Order filter. The reference design includes the RTL VHDL implementation of an efficient sorting algorithm.
|
1.1 |
431 KB |
09/21/2006 |
XAPP689 - Managing Ground Bounce in Large FPGAs (PDF)
View Document Details
Ground bounce must be controlled to ensure proper operation of high performance FPGA devices. Particular attention must be applied to minimizing board-level inductance during PCB layout. This document describes calculations that help to ensure that a design meets input undershoot and logic-low voltage requirements for devices receiving signals from an FPGA.
|
1.2 |
90 KB |
10/30/2007 |
XAPP659 - Virtex-II Pro / Virtex-II Pro X 3.3V I/O Design Guidelines (PDF)
View Document Details
This application note describes how to interface 3.3V I/O in a Virtex™-II Pro system design. Topics include using the LVDCI_33 I/O standard to interface to LVCMOS or LVTTL external interfaces, Peripheral Component Interface (PCI) bus interface solutions, device configuration, and other board-level design techniques. Was this document helpful? Yes | No
|
1.7 |
419 KB |
04/24/2007 |
XAPP646 - Connecting Virtex-II Devices to a 3.3V/5V PCI Bus (PDF)
View Document Details
This application note describes how to connect Virtex™-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan™-3, and Spartan-3E devices to 3.3V or 5V PCI buses. The design responds to customer demand for a general solution for applications with a Virtex-II device and a 5V PCI bus, as well as for applications with a Virtex-II Pro, Virtex-4, Virtex-5, Spartan-3, or Spartan-3E device and a 3.3V or 5V PCI bus. Was this document helpful? Yes | No
|
1.2.2 |
65 KB |
04/23/2007 |
XAPP623 - Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors (PDF)
View Document Details
This application note covers the principles of power distribution systems and bypass or decoupling capacitors. A step-by-step process is described where a power distribution system can be designed and verified. The final section discusses additional sources of power supply noise and provides resolutions.
|
2.1 |
437 KB |
02/28/2005 |
XAPP1002 - Using ChipScope Pro to Debug Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE (PDF)
View Document Details
This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI
Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.
|
1.0 |
1.27 MB |
10/22/2007 |
XAPP1022 - Using MET with PIO Example Design for PCI Express Endpoint Cores (PDF)
View Document Details
This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with the Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE for PCI Express® Xilinx solutions.
|
1.0 |
1.19 MB |
09/19/2007 |
XAPP696 - Interfacing LVPECL 3.3V Drivers with Xilinx 2.5V Differential Receivers (PDF)
View Document Details
This application note describes how to interface 3.3V differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) drivers with Xilinx® 2.5V differential receivers, including Virtex®-II Pro, Virtex-II Pro X, Virtex-4, Virtex-5, Spartan®-3E, and Spartan-3 FPGA 2.5V LVPECL and Low Voltage Differential Signaling (LVDS). Several interface modifications are presented with supporting IBIS simulation results. Was this document helpful? Yes | No
|
1.3 |
324 KB |
05/01/2008 |
XAPP868 - Clock Data Recovery Design Techniques for E1/T1 Based on Direct Digital Synthesis (PDF)
View Document Details
This document details the design aspects of digital PLLs implemented in Virtex® and Spartan® FPGAs for telecommunications applications. PLL performance and loop stability are evaluated.
|
1.0 |
287 KB |
01/29/2008 |
XAPP459 - Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Generation FPGAs (PDF)
View Document Details
This application note describes solutions to receive large-swing signals by design. In one solution (and in the general case of severe positive and/or negative overshoot), parasitic leakage current between User I/O in differential pin pairs may occur, even though the User I/O pins are configured with single-ended I/O standards. This application note addresses the parasitic leakage current behavior. Was this document helpful? Yes | No
|
1.0 |
457 KB |
04/18/2008 |
XAPP469 - Spread-Spectrum Clocking Reception for Displays (PDF)
View Document Details
Describes how Extended Spartan®-3A family and Spartan-3E FPGAs work in spread-spectrum applications.
Was this document helpful? Yes | No
|
1.0 |
347 KB |
08/22/2008 |
XAPP058 - Xilinx In-System Programming Using an Embedded Microcontroller (PDF)
View Document Details
The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.
|
4.1 |
641 KB |
03/06/2009 |
XAPP483 - Multiple-Boot with Platform Flash PROMs (PDF)
View Document Details
This Application Note describes the feature of Platform Flash PROMs that allows the user to Multiple-Boot or dynamically reconfigure from up to four Design Revisions.
|
2.0.1 |
280 KB |
11/19/2007 |
XAPP500 - J Drive: In-System Programming of IEEE Standard 1532 Devices (PDF)
View Document Details
The J Drive programming engine provides immediate and direct in-system configuration (ISC) support for IEEE Standard 1532 programmable logic devices (PLDs). To configure an in-system device, the programming engine uses the configuration algorithm information from a 1532 Boundary Scan Description Language (BSDL) file to apply configuration data from the 1532 data file through the IEEE Standard 1149.1 test access port (TAP). The J Drive executable, source code, and a programming example are available in a download package from the Xilinx website. The J Drive programming engine can be used for the following Xilinx families: CoolRunner-II CPLDs, XC9500/XL/XV CPLDs, Spartan-3 Generation FPGAs, and Virtex-II (and later) series FPGAs.
|
2.1.2 |
122 KB |
11/12/2007 |
XAPP457 - Powering and Configuring Spartan-3 Generation FPGAs in Compliant PCI Applications (PDF)
View Document Details
The PCI™ Local Bus Specification defines a number of power and reset requirements. When considered in an FPGA implementation, these create several challenges that must be addressed for long term reliability and broad interoperability. This application note applies to compliant PCI applications using Spartan™-3 Generation FPGAs, and is relevant to other Xilinx FPGA families, as well as related PCI applications.
|
1.0 |
170 KB |
06/08/2007 |
XAPP228 - Quad-Port Memories in Virtex Devices (PDF)
View Document Details
This application note describes how the existing dual-port block memories in the Spartan®-II and Virtex® families can be used as Quad-Port memories. This essentially involves a data access time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the block memory in terms of bits per second will remain the same.
|
1.0 |
61 KB |
09/24/2002 |
XAPP291 - Self-Addressing FIFO (PDF)
View Document Details
The block memories in the Virtex®-II architecture are capable of supporting data bus widths of up to 36-bits. A self-addressing FIFO reference design uses these block memories to store both data and address information in a single memory location. This application note describes FIFO designs where no external counters are required. Only flag and status information logic is used. The resulting FIFOs are not fast (around 150 MHz). Their advantage is in using only one clock load. In addition, the status mechanism is very simple making FIFOs are more suitable for data throttling in continuous data systems instead of the full or empty detection required in frame-based data systems.
|
1.3 |
101 KB |
06/03/2005 |
XAPP503 - SVF and XSVF File Formats for Xilinx Devices (PDF)
View Document Details
This application note provides users with a general understanding of the SVF and XSVF file formats as they apply to Xilinx® devices. Some familiarity with IEEE STD 1149.1 (JTAG) is assumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format (XSVF) files in embedded programming applications, refer to Xilinx Application Note XAPP058. Was this document helpful? Yes | No
|
2.1 |
372 KB |
08/17/2009 |
XAPP502 - Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode (PDF)
View Document Details
In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.
|
1.6.1 |
356 KB |
08/24/2009 |
XAPP1015 - Audio/Video Connectivity Solutions for Spartan-3E FPGAs (PDF)
View Document Details
This application note describes how to use Spartan®-3E FPGAs to implement various serial digital video interfaces commonly used in the professional video broadcast industry.
|
01 |
4.9 MB |
09/28/2009 |