Spartan-3E Application Notes

This application note describes how to build a system that can be used for determining the optimal phase shift for a DDR memory feedback clock. In this system, the DDR memory is controlled by a controller that attaches to either the OPB or PLB and is used in an embedded microprocessor application. This reference system also uses a DCM that is configured so that the phase of its output clock can be changed while the system is running and a GPIO core that controls that phase shift. The GPIO output is controlled by a software application that can be run on a PPC or MicroBlaze™ microprocessor

Design File(s):

• xapp806_MB_ph_shift.zip
• xapp806_PPC_ph_shift.zip

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

Differential signals, such as LVDS or LVPECL, can be difficult to route on simple, four-layer or six-layer PCBs without excessive use of vias. This application note shows how Spartan™-3 Generation FPGAs, with just the inclusion of an inverter in the datapath, can avoid excessive use of vias and fix accidental PCB trace swapping without requiring a PCB respin.

Design File(s):

• xapp491.zip
• xapp491.zip

XAPP482 describes a working MicroBlaze™ system that stores software code, user data, and configuration data in non-volatile Platform Flash PROMs, simplifying system design and reducing cost. It provides a portable hardware design, software design, and additional script utilities to be used during the implementation flow.

Design File(s):

• xapp482.zip
• xapp482.zip

For the latest version of this application note, see the BSDL chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

For the latest version of this application note, see the Multiplexers chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

Design File(s):

• xapp466_vhdl.zip
• xapp466_verilog.zip

For the latest version of this application note, see the SRL16 chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

Design File(s):

• xapp465_vhdl.zip
• xapp465_verilog.zip

For the latest version of this application note, see the Distributed RAM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

Design File(s):

• xapp464_vhdl.zip
• xapp464_verilog.zip

For the latest version of this application note, see the Block RAM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

Design File(s):

• xapp463_verilog.zip
• xapp463_vhdl.zip

For the latest version of this application note, see the DCM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

Design File(s):

• xapp462_verilog.zip
• xapp462_vhdl.zip

The PCI specification defines two I/O timing budgets for use with 33 MHz and 66 MHz operation. In embedded designs, custom timing budgets enable the following: • Reduce total system cost by using less expensive devices • Achieve higher data transfer rates than allowed by specification • Add more loads to the bus to accommodate additional devices and connectors • Increase the physical length of the bus to accommodate novel bus topologies The information presented in this application note is applicable to any embedded PCI implementation using Xilinx FPGA devices.

This application note describes how memories wider than 36 bits can be efficiently implemented in the Virtex™-II and Spartan™-3 architectures. The clock-doubling method used is similar to the method described for quad-port memories in XAPP228. The resulting memories are used in either dual-port or single-port mode.

Design File(s):

• xapp229.zip
• xapp229.zip

When designing digital systems, there is often a requirement to synchronize incoming data and clock signals with an internal system clock, i.e., the internal and external clock are at exactly the same frequency, but due to variable backplane, board, or application-specific standard product (ASSP) delays, the phase relationship is not known. The circuit described in this application note addresses this issue for both single traces and data buses up to 210 MHz in a Virtex®-II -5 device. The speed limitation is imposed by the maximum frequency that can be accepted by the Digital Clock Manager (DCM), in a mode where it is capable of providing both a new clock and a new clock shifted by 90 degrees.

Design File(s):

• xapp225.zip

Data recovery is a mechanism that allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts this information from the data stream concerned, but sometimes the receiver’s clock is used for data transmission. The circuit described in this application note provides a partial solution at data rates up to 160 Mb/s in a Virtex™-E -7 device, a Spartan™-IIE -6 device, or a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro™ -6 device. The solution is partial in the sense that no clock is actually recovered, but the data arriving is fully extracted. The speed is limited by the maximum frequency that can be accepted by the Delay Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock, and another clock shifted by 90 degrees.

Design File(s):

• xapp224.zip
• xapp224.zip

This application note describes an approach to the 3.3V configuration of Spartan®-3 FPGAs. It provides a set of proven connection diagrams for each configuration mode. The same approach can be applied to the Spartan-3E family.

This application note addresses low-cost, four- to six-layer, high-volume printed circuit board (PCB) layout for a Spartan™-3E FPGA in the FT256 1 mm BGA package. Intended for design engineers, managers, and PCB layout staff, who are already familiar with SI related design issues. The general guidelines can be used to optimize board layout for other devices and packages.

Design File(s):

• xapp489.zip
• xapp489.zip

This application note describes techniques for remote reconfiguration of FPGAs through an Ethernet port.

Design File(s):

• xapp441_designfiles.zip
• xapp441_designfiles.zip

Hot-swapping or hot insertion describes a potentially dangerous method of inserting an unpowered board into a power-on (hot) running system. There are several concerns: the insertion must not cause physical harm or permanent damage to the system or the inserted board, and the insertion must not cause data corruption or any transient system upsets. This application note describes the physical aspects of hot-inserting a Virtex™-II based card into a system or system backplane, using sequenced connectors, where VCC and GND mate well before any signal pins can mate. The dangers of using normal non-sequenced connectors are described in Hot Plug-In. Not addressed in this application note are system issues including detecting the presence or absence of a card, or how the card is accepted in the system.

Using and Creating Flash Files for MicroBlaze™.

This is a reference design for the Spartan™-3E Display Development Kit to assist in developing display panel products. The display solution FPGA design consists of a Video Input interface, Color Temperature Correction, Precise Gamma Correction, Image Dithering Engine, and an output interface.

Design File(s):

• xapp928.zip

This application note discusses the use of Partitions in the Incremental Design Flow. It is recommended that module instances with high logic density, timing critical paths, or timing critical module instances be designated Partitions.

This application note describes the implementation of a two-dimensional Rank Order filter. The reference design includes the RTL VHDL implementation of an efficient sorting algorithm.

Design File(s):

• xapp953.zip

Ground bounce must be controlled to ensure proper operation of high performance FPGA devices. Particular attention must be applied to minimizing board-level inductance during PCB layout. This document describes calculations that help to ensure that a design meets input undershoot and logic-low voltage requirements for devices receiving signals from an FPGA.

Design File(s):

• xapp689.zip

This application note describes how to connect Virtex™-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan™-3, and Spartan-3E devices to 3.3V or 5V PCI buses. The design responds to customer demand for a general solution for applications with a Virtex-II device and a 5V PCI bus, as well as for applications with a Virtex-II Pro, Virtex-4, Virtex-5, Spartan-3, or Spartan-3E device and a 3.3V or 5V PCI bus.

This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.

Design File(s):

• xapp1002.zip

This application note describes how to interface 3.3V differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) drivers with Xilinx® 2.5V differential receivers, including Virtex®-II Pro, Virtex-II Pro X, Virtex-4, Virtex-5, Spartan®-3E, and Spartan-3 FPGA 2.5V LVPECL and Low Voltage Differential Signaling (LVDS). Several interface modifications are presented with supporting IBIS simulation results.

This document details the design aspects of digital PLLs implemented in Virtex® and Spartan® FPGAs for telecommunications applications. PLL performance and loop stability are evaluated.

Design File(s):

• xapp868.zip

Describes how Extended Spartan®-3A family and Spartan-3E FPGAs work in spread-spectrum applications.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

Design File(s):

• xapp058.zip

This Application Note describes the feature of Platform Flash PROMs that allows the user to Multiple-Boot or dynamically reconfigure from up to four Design Revisions.

Design File(s):

• xapp483.zip

The J Drive programming engine provides immediate and direct in-system configuration (ISC) support for IEEE Standard 1532 programmable logic devices (PLDs). To configure an in-system device, the programming engine uses the configuration algorithm information from a 1532 Boundary Scan Description Language (BSDL) file to apply configuration data from the 1532 data file through the IEEE Standard 1149.1 test access port (TAP). The J Drive executable, source code, and a programming example are available in a download package from the Xilinx website. The J Drive programming engine can be used for the following Xilinx families: CoolRunner-II CPLDs, XC9500/XL/XV CPLDs, Spartan-3 Generation FPGAs, and Virtex-II (and later) series FPGAs.

Design File(s):

• xapp500.zip

The PCI™ Local Bus Specification defines a number of power and reset requirements. When considered in an FPGA implementation, these create several challenges that must be addressed for long term reliability and broad interoperability. This application note applies to compliant PCI applications using Spartan™-3 Generation FPGAs, and is relevant to other Xilinx FPGA families, as well as related PCI applications.

Design File(s):

• xapp457.zip

This application note describes how the existing dual-port block memories in the Spartan®-II and Virtex® families can be used as Quad-Port memories. This essentially involves a data access time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the block memory in terms of bits per second will remain the same.

Design File(s):

• xapp228.zip

The block memories in the Virtex®-II architecture are capable of supporting data bus widths of up to 36-bits. A self-addressing FIFO reference design uses these block memories to store both data and address information in a single memory location. This application note describes FIFO designs where no external counters are required. Only flag and status information logic is used. The resulting FIFOs are not fast (around 150 MHz). Their advantage is in using only one clock load. In addition, the status mechanism is very simple making FIFOs are more suitable for data throttling in continuous data systems instead of the full or empty detection required in frame-based data systems.

Design File(s):

• xapp291.zip

This application note provides users with a general understanding of the SVF and XSVF file formats as they apply to Xilinx® devices. Some familiarity with IEEE STD 1149.1 (JTAG) is assumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format (XSVF) files in embedded programming applications, refer to Xilinx Application Note XAPP058.

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

Design File(s):

• xapp502.zip

This application note describes how to use Spartan®-3E FPGAs to implement various serial digital video interfaces commonly used in the professional video broadcast industry.

Design File(s):

• xapp1015.zip

This application note describes the implementation of a YCrCb color space to an RGB Color space conversion circuit necessary in many video designs.

Design File(s):

• xapp931.zip

This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with all Xilinx solutions for PCI Express®.

Design File(s):

• xapp1022.zip

This application note contains guidelines on reflow soldering, inspection, and rework process for Pb-free packages.

This application note describes a cost-optimized copy protection scheme that helps protect an FPGA against cloning. The design leverages an external secure serial EEPROM. The included reference design uses an optimized PicoBlaze™ 8-bit microcontroller. This application note provides a hardware design with associated PicoBlaze software code. The code loads a secret key into the secure EEPROM and authenticates the user system with the secure EEPROM.

Design File(s):

• xapp780.zip

This application note targets Spartan®-3E/3A devices in applications that require 4-bit or 5-bit receive data bus widths and operate at rates up to 666 Mbps per line with a clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

Design File(s):

• xapp485.zip

This application note targets Spartan™-3E devices in applications that require 4-bit or 5-bit transmit data bus widths and operate at rates up to 666 Mbps per line with a forwarded clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

Design File(s):

• xapp486.zip
• xapp486.zip

This application note describes the implementation of six circuits necessary to perform commonly used conversions between various chroma formats. It is accompanied by reference designs which include Generic RTL VHDL code.

Design File(s):

• xapp932.zip

This application note describes solutions to receive large-swing signals by design. In one solution (and in the general case of severe positive and/or negative overshoot), parasitic leakage current between User I/Os in differential pin pairs may occur, even though the User I/O pins are configured with single-ended I/O standards. This application note addresses parasitic leakage current behavior.

This application note discusses how to design and implement a Bus Master design using Xilinx® Endpoint PCI Express® solutions. A performance demonstration reference design using Bus Mastering is included with this application note. The reference design can be used to gauge achievable performance in various systems and act as a starting point for an application-specific Bus Master Direct Memory Access (DMA). The reference design includes all files necessary to target the Integrated Blocks for PCI Express on the Virtex®-6 and Spartan®-6 FPGAs, the Endpoint Block Plus Wrapper Core for PCI Express using the Virtex-5 FPGA Integrated Block for PCI Express, and the Endpoint PIPE for PCI Express targeting the Xilinx Spartan®-3 family of devices.

Design File(s):

• xapp1052.zip