Constraints Entry Methods

ISE

Following are the most commonly used methods of entering constraints:

User Constraints File (UCF), using one of the following tools:
- Constraints Editor
- ISE Text Editor
- PlanAhead™ software (for FPGAs)
- Pinout and Area Constraints Editor (PACE) (for CPLDs)
- Commercially available text editors
HDL source file using a text editor
XST Constraint File (XCF) using a text editor

Each method allows you to specify most constraints, but certain methods are recommended over others in different situations, as described in the following sections.

Note See the "Entry Strategies for Xilinx Constraints" chapter of the Constraints Guide for detailed information on all of the constraint entry methods. See the "Xilinx Constraints" chapter for the entry methods supported for each constraint.

Constraints Entry Tools

Each constraints entry tool is recommended for different situations as follows:

Constraints Editor
Constraints Editor is the recommended tool for entering timing constraints in most situations. After synthesis, this tool lists all the elements and nets in the design. It allows you to group common elements and nets as well as specify constraints for specific nets. It is not necessary to know the Xilinx® constraint syntax, because the tool enters the appropriate constraints based on the feedback you provide. For more information about Constraints Editor, see the Constraints Editor Help. In the Help Viewer, click the Synchronize TOC button to view all related Help topics.
PlanAhead software or PACE
You can use PlanAhead (for FPGAs) or PACE (for CPLDs) either before or after synthesis. Using a drag-and-drop approach, you can enter placement constraints, including pinout constraints, logic placement, and area constraints. For more information, see the PlanAhead User Guide or PACE Help.
Text Editor
Hand editing the constraints file is recommended for modifying design constraints to meet changing timing requirements and for creating multiple versions of the constraints file for testing how different constraints affect the design. You can specify your preferred text editor in the Editors page of the Preferences dialog box.

Note Names of objects in the design, such as net names, must exactly match the case of the name as it exists in the source design netlist, either uppercase or lowercase. Entering constraints in all uppercase is recommended, for example, LOC, NET, INST.

UCF File Constraints

UCF file constraints are used during the implementation process. You can enter timing and placement constraints in the UCF file. In Project Navigator, you can edit your UCF file using any of the following methods:

In the Hierarchy pane of the Design panel, double-click the UCF file.
Modify the UCF file in the tool you specified in the Constraints entry editor field of the Editors page of the Preferences dialog box.
In the Hierarchy pane of the Design panel, select the UCF file. In the Processes pane, expand User Constraints, and double-click Edit Constraints (Text).
Modify constraints in a text editor. This method is recommended for quick, minor modifications. For more information, see Creating and Editing Constraints in a Text Editor.
In the Hierarchy pane of the Design panel, select the top module. In the Processes pane, double-click any of the following User Constraints processes, which automatically open the UCF file in the appropriate constraints entry tool for the process:
- Create Timing Constraints
  Modify timing constraints in the Constraints Editor. For more information, see Creating Timing Constraints with Constraints Editor.
- I/O Pin Planning (PlanAhead) - Pre-Synthesis (for FPGAs) or Floorplan IO - Pre-Synthesis (for CPLDs)
  Modify pinout constraints in the PlanAhead software (for FPGAs) or PACE (for CPLDs). For more information, see I/O Pin Planning – Pre-Synthesis.
- I/O Pin Planning (PlanAhead) - Post-Synthesis (for FPGAs)
  Modify pinout constraints in the PlanAhead software. For more information, see I/O Pin Planning – Post-Synthesis.
- Floorplan Area/IO/Logic (PlanAhead) (for FPGAs)
  Modify area constraints in the PlanAhead software. For more information, see Floorplanning a Design – Post-Synthesis.
Note Alternatively, you can use the Tools menu to select these commands.
In the Hierarchy pane of the Design panel, select the top module. In the Processes pane of the Design panel, expand the Place & Route process, and double-click Analyze Timing/Floorplan Design (PlanAhead).
Modify area constraints in the PlanAhead software. For more information, see Analyzing Timing and Floorplanning a Design — Post-Implementation.
Note Alternatively, you can use the Tools menu to select this command.

Multiple UCF Files

To organize constraints, you can assign multiple UCF files to a top-level module in your design. To add or create a UCF file, select the top module in the Hierarchy pane of the Design panel, and select either Project > Add Source or Project > New Source. UCF files appear in the Hierarchy pane. When you implement your design, constraints from all of the UCF files are applied. Constraints are applied in order, starting with the first UCF file you added to your project.

Note When constraints editing tools are automatically launched, such as the PlanAhead software, you are prompted to select which UCF file to edit.

HDL File Constraints

The VHSIC Hardware Description Language (VHDL) and Verilog hardware description languages (HDLs) allow you to embed constraints in the design code at the highest level of abstraction. This method is recommended for constraints that define the desired result of the HDL (FSM_ENCODING, MULT_STYLE) or specific optimization (REGISTER_DUPLICATION, MAX_FANOUT). This method offers the following advantages:

Ability to retain constraints throughout the design flow
During synthesis, net names in the HDL code are commonly changed to a new name chosen by the synthesis tool. The new name may vary depending on the synthesis tool and may even vary across synthesis runs using the same synthesis tool. Specifying the timing of the net within the HDL code allows the constraint to be applied consistently throughout the design, regardless of the net names assigned by the synthesis tool.
Support for recursive structures
Recursive structures are commonly used to instantiate device-specific components based on design parameters. By defining a common timing constraint for each generated structure, constraint definitions are independent of the final design implementation.
Ease of maintenance for complex design constraints
The high-level, generic nature of HDL-defined timing constraints simplifies the overhead required to maintain complex design constraints.
Reuse
Entering constraints in the HDL allows you to reuse the constraints code in other designs.

Note See the "Entry Strategies for Xilinx Constraints" chapter of the Constraints Guide for detailed information on VHDL and Verilog constraints.

XCF File Constraints

You can use the XST Constraint File (XCF) when using Xilinx Synthesis Technology (XST) as your synthesis tool. This file is typically used for entering the following constraints:

Timing constraints for XST
Synthesis constraints (when you want to keep the constraints separate from the HDL file)

Although XST automatically optimizes the design for timing performance during synthesis, adding timing constraints specifically for synthesis may help improve performance. If you enable the Write Timing Constraints Synthesis Option in the Process Properties dialog box, these timing constraints are also passed on to the ISE® implementation tools.

Note See the "Design Constraints" chapter of the XST User Guide for more information on the use of constraints in the XCF file.

To create and modify the XCF file, you must use a text editor. To use the XCF constraints in your design, you must specify the XCF file using the following Synthesis Options in the Process Properties dialog box:

Synthesis Constraints File - Browse and select the XCF file.
Use Synthesis Constraints File - Make sure this option is selected.

Note To open the Process Properties dialog box, right-click the Synthesize - XST process, and select Process Properties. For more information, see Setting Process Properties.