Floorplanning and Assigning Placement Constraints with PlanAhead Software

ISE

When targeting FPGAs, you can use the PlanAhead™ software to enter placement constraints that control I/O pin and logic assignments, global logic placement, and area group assignment. The PlanAhead software provides a comprehensive environment for analyzing the design for connectivity, density, and timing. After analyzing the design, you can apply placement constraints to help drive the implementation tools toward improved results. These constraints may include location constraints to lock specific logic objects into specific sites on the device or area constraints to constrain a group of logic within a specific area of the device.

Note When you invoke the PlanAhead software from Project Navigator, a simplified version of the software is launched. The standalone version of the PlanAhead software has additional features. For more information on the PlanAhead software, see the PlanAhead User Guide. For more information on constraints, see the "Constraint Types" chapter of the Constraints Guide.

Launching PlanAhead Software from Project Navigator

You can launch the PlanAhead software from Project Navigator to floorplan and assign placement constraints. In the Processes pane of the Design panel, double-click the following processes. Alternatively, you can select these items as menu commands from the Tools menu:

Floorplan Area/IO/Logic (PlanAhead)
For more information, see Floorplanning a Design — Post-Synthesis.
Note To access this process from the Processes pane, expand the User Constraints process.
Analyze Timing/Floorplan Design (PlanAhead).
For more information, see Analyzing Timing and Floorplanning a Design — Post-Implementation.
Note To access this process from the Processes pane, expand the Implement Design process and then, Place & Route.

Caution! When using the PlanAhead software, avoid making updates to source files in Project Navigator to prevent data mismatch.

Placement Constraint Assignment

The PlanAhead software allows you to lock down logic to specific device sites. This often includes global logic objects such as the following: BUFG, BRAM, MULT, PPC405, GT, DLL, and DCM. To place logic objects, you can drag the logic object from the various PlanAhead software views, and drop it in the Device View in the Workspace. For some types of logic, such as I/O ports, you can enter the location site in the object General Properties view.

Area Group Assignment

Area groups are the primary means of placing logic in specific regions of the device, for example, within a particular clock region. The PlanAhead software allows you to create area groups using various methods. The software assists with connectivity, size logic types, and ranges, including design rule checks (DRCs) to ensure proper AREA_GROUP property definitions.

Additional Resources

Additional information is available from the following Xilinx® documentation:

Documentation	Topics Covered
“Analyzing the Design,” “Analyzing Implementation Results,” and “Floorplanning the Design” chapters of the PlanAhead User Guide	Information on using the PlanAhead software for assigning placement constraints and creating area group constraints.
Constraints Guide	Constraint types, entry methods supported for each constraint, and a listing of all constraints