Creating a Custom Compile File for Simulation

ISE

Caution! Overriding the default compile order may break your design flow or lead to unpredictable results. Only use this procedure if the default compile list appears incorrect, and you need to manually override the compile order.

You can create a custom compile file to override the default simulation compile order as follows.

Note This is an option when using the ModelSim and ISim simulators only.

To Create a Custom Compile File for Simulation

Create a text file in your project directory that contains a list of the file names to compile, including the library in which they reside. Enter the file names in the order you want them compiled. The format is as follows:

library_name;file_name

For example:

work;myfile1.vhd

work;..\shared_files\myfile2.vhd

mylib;..\shared_files\mypackage.vhd

Following are general rules for creating this file:

Each library and file pair must be separated by a semicolon (;).
You must specify a library. This is required.
Note For Verilog files, you must specify the work library. You cannot create your own Verilog libraries.
Only specify HDL files. Other source types, such as schematics, are not converted to HDL.

To Use the Custom Compile File

In the Design panel, select Behavioral Simulation from the Design View drop-down list.
In the Hierarchy pane, select the source file to simulate.
In the Processes pane, expand ISim Simulator or ModelSim Simulator.
Right-click Simulate Behavioral Model or Generate Self-Checking Test Bench, and select Process Properties.
In the Process Properties dialog box, set the Property display level to Advanced.
Enable the Use Custom Project File option.
In the Custom Project Filename field, enter the name of your custom compile file or browse to the file.
Click OK.

Your custom compile file is used to generate the compile instructions for simulation instead of the default compile list.