Memory Use and Runtime Strategies for FPGAs

ISE

Following is information on the maximum memory available per operating system:

Windows XP Professional/Vista Business (32-bit)
Standard Windows-based operating systems have a limit of 2 gigabytes (GB) for memory use for a single process. This limit may cause memory issues when running large Xilinx® designs, for example, when implementing the design with aggressive timing constraints or when manipulating the design in the FPGA Editor. If you are using a 32-bit Windows XP Professional operating system, you can increase this limit to 3 GB in a system that has 4 GB of RAM or more. Modify your boot.ini file by adding /3GB to the end of the >startup line.
Windows XP Professional/Vista Business (64-bit)
Typically, 64-bit systems require approximately 60% more memory than 32-bit systems. However, these systems can accommodate for very large process sizes, beyond what a single ISE® software process would need. This operating system provides greater than 3 GB of memory.
Red Hat Enterprise Linux 5 or SuSE Linux Enterprise 10 (32-bit)
The 32-bit Linux operating systems allow you to use up to approximately 3 GB of memory in a system that has 4 GB of RAM or more.
Red Hat Enterprise Linux 5 or SuSE Linux Enterprise 10 (64-bit)
ISE software runs 64-bit Linux on X86-64 processors, such as Advanced Micro Devices, Inc. (AMD) Opteron and Intel Xeon. This operating system provides greater than 3 GB of memory.

Constraints Strategies

To reduce memory usage, examine your timing constraints as follows:

Use global timing constraints.
Use global timing constraints, such as the PERIOD constraint, whenever possible. Limit the number of FROM-TO constraints. When using FROM-TO constraints, avoid using generic timing groups, such as FFS, because they consume a large amount of memory. Use the TIMEGRP constraint within the FROM-TO constraints. For more information on constraints, see Timing Constraints Strategies.
Do not over-constrain your design.
For example, do not place a 120 megahertz (MHz) constraint on a 100 MHz clock. Over-constraining your design usually increases memory use and runtime without increasing the performance of the design.
Combine similar timespecs that have the same timing requirement.
For example, if a 64-bit bus has 64 different OFFSET constraints, you can save memory by combining the constraints into a single OFFSET constraint that covers the entire bus.
When creating TIMEGRPs for multi-cycle paths or TIG constraints, group elements using the clock signal or a clock enable signal.
A TIMEGRP must only have synchronous elements with the same clock. Do not use the generic timing group FFS with different clocks in the same TIMEGRP. Instead, make the TIMEGRP as complete as possible. For example, if FFA, FFB, and FFC all go to FFD, then FFA, FFB, and FFC should all be in the source TIMEGRP if they are all clocked by the same clock.

Note For detailed information on these constraints, see the "Xilinx Constraints" chapter of the Constraints Guide.

Map and Place and Route Strategies

If memory problems persist, examine your map or place and route settings as follows:

If your timing constraints are relaxed and the placer and router can meet your timing objectives, set the Map Effort Level and Place & Route Effort Level (Overall) to Standard (-ol std) rather than High (-ol high).
Avoid using the Map and Place & Route Extra Effort properties (-xe) unless absolutely necessary.
Avoid using the physical synthesis Map properties. These include the following: Global Optimization (-global_opt), Retiming (-retiming), Register Duplication (-register_duplication), and Combinatorial Logic Optimization (-logic_opt).

You can set Map properties using either of the following methods:

Project Navigator - Map Properties
Command line - MAP options. For details, see the "MAP Options" section in the "MAP" chapter of the Command Line Tools User Guide.

You can set Place and Route properties using either of the following methods:

Project Navigator - Place & Route Properties
Command line - PAR options. For details, see the "PAR Options" section in the "PAR" chapter of the Command Line Tools User Guide.