Design Performance Techniques for FPGAs

ISE

The following strategies can help you achieve performance, as well as decrease your overall design time and implementation runtime.

Reasonable Performance Objectives

Set reasonable performance objectives as follows:

Ensure that your performance objectives match the device.
You must select a device that can achieve the clock speeds needed for your design. For information on how to determine device utilization, see the "Evaluating Design Size and Performance" section in the "Understanding High-Density Design Flow" chapter of the Synthesis and Simulation Design Guide.
Evaluate levels of logic.
If your HDL code produces too many levels of logic, you may not be able to meet your timing objectives. Propagation delays may be minimal, but the routing delays may jeopardize your ability to meet your timing objectives. See the "Evaluating Coding Style and System Features" section in the "Understanding High-Density Design Flow" chapter of the Synthesis and Simulation Design Guide.

I/O Placement Locking

Place your inputs and outputs so that the data path is flowing left to right or right to left. This helps the placer and router understand the structure of the data. This reduces the complexity of the placing and routing and may also reduce the amount of resources used.

Note For FPGA designs, use the PlanAhead™ software to place your inputs and outputs. For more information, see I/O Pin Planning with PlanAhead Software.

Timing-Driven Packing and Placement

The preferred method for running Map is to use the Perform Timing-Driven Packing and Placement property. Running Map with default settings packs logic by connectivity, while running Map with this property packs logic by timing requirements. As a result, this property may decrease unrelated packing and achieve performance. It increases Map runtime but may help your design meet timing objectives, which would otherwise not be met during Place and Route. For the best placement, use this property with the Place & Route Effort Level (Overall) set to High (par -ol high).

You can set this property using either of the following methods:

Project Navigator - Perform Timing-Driven Packing and Placement Map Property
Note This property is only available when you set the Property display level to Advanced.
Command line - map -timing option. For details, see the “MAP Options” section in the “MAP" chapter of the Command Line Tools User Guide.

Note For Virtex-5 devices, the Perform Timing-Driven Packing and Placement property is always used. Therefore, it is not available as a Map Property in the Process Properties dialog box, and you do not need to specify map -timing from the command line.

Effort Levels for Map and Place and Route Properties

Initially, use the Standard effort level for both Map and Place and Route. If your timing objectives are not met after using the default Standard setting, try different combinations the Effort Level settings to improve performance. Performance can be focused on placement objectives, timing objectives, or both.

You can control the effort levels using either of the following methods:

Project Navigator - Map Properties and Place & Route Properties
Note To use the Map Effort Level property, you must enable the Perform Timing-Driven Packing and Placement property.
Command line - -ol option. For details, see the “MAP Options” section in the “MAP” chapter and the PAR Options" section in the "PAR" chapter of the Command Line Tools User Guide.

The following table shows when to use the different effort level settings.

Map Effort Level	Place and Route Effort Level (Overall)	When to Use
Standard or map -timing -ol std Note To use the Map Effort Level property, you must enable the Perform Timing-Driven Packing and Placement property.	Standard or par -ol std	Use these default settings in the following situations: On the initial design run to assess potential problems in the design. This ensures that runtime is kept to a minimum while you assess your design. For example, place and route your design using the Standard setting, and then run Timing Analyzer or TRACE to assess whether you have a critical path with too many levels of logic. If this is the case, you can modify your Hardware Description Language (HDL) file to reduce the levels of logic. For details, see the "Evaluating Coding Style and System Features" section in the "Understanding High-Density Design Flow" chapter of the Synthesis and Simulation Design Guide. To discover packing issues that can be fixed using mapping properties. For details on the Project Navigator properties, see Map Properties. For details on the corresponding command line options, see the "Map Options" section of the "MAP" chapter in the Command Line Tools User Guide. Note You can use these default settings and enable the Ignore User Timing Constraints property (-x option). The design enters the "Performance Evaluation Mode" when the Ignore User Timing Constraints property is enabled or when no constraints are specified. In this mode, the performance on each clock is optimized automatically. This mode is useful to evaluate the performance that can be attained on the design without having to constrain each clock.
Not set	High or par -ol high	This combination only applies to Virtex-4, Spartan®-3, Spartan-3A and Spartan-3E devices only.
High or map -timing -ol high	Standard or par -ol std	Use this combination if the design is highly utilized or if timing constraints are difficult to meet. Having a higher quality placement can dramatically reduce the time needed to route and meet timing, resulting in an overall runtime reduction.
High or map -timing -ol high	High or par -ol high	Use this combination when the design has aggressive timing, and placement and routing requires High effort levels to meet timing objectives.

Extra Effort Level

Extra Effort performs additional optimization to improve timing performance, but can significantly increase runtime and does not guarantee better results. Extra Effort is not recommended as a default setting and is not recommended when the design is unstable.

You can set Extra Effort using either of the following methods:

Project Navigator - Map Properties and Place & Route Properties
Note You can only modify the Extra Effort Level if the Map Effort Level or Place & Route Effort Level (Overall) is set to High. In addition, this property is only available when you set the Property display level to Advanced.
Command line - -xe option. For details, see the “MAP Options” section in the “MAP” chapter and the PAR Options" section in the "PAR" chapter of the Command Line Tools User Guide.
Note On the command line, you can only set map -xe or par -xe when also setting -ol high.

Map Properties

You can use various Map properties to assist with physical synthesis and improve design performance.

You can set Map properties using either of the following methods:

Project Navigator - Map Properties
Command line -: MAP options. For details, see the "MAP Options" section in the "MAP" chapter of the Command Line Tools User Guide.

Note Some of these properties are only available when you set the Property display level to Advanced.

The following table shows when to use the different Map properties.

Map Property	When to Use
Global Optimization or -global_opt	Use this property to perform global optimization routines on the fully assembled netlist before mapping the design. The use of Global Optimization is most effective when designs are built from multiple netlists (including IP cores) or when the full set of optimization techniques are not utilized during the synthesis phase. Depending on the value set, this property optimizes for speed, area, or power. When optimizing for area or power, there may be a trade-off in timing performance. Note This property is supported for Virtex®-4 and Virtex-5 devices only.
Retiming or -retiming	Use this property to move registers forward or backwards through the logic to balance out the delays in a timing path to increase the overall clock frequency. The overall number of registers may be altered due to the processing. By default, this option is off. Note This property is supported for Virtex-4 and Virtex-5 devices only. This option is available only when Global Optimization (-global_opt) is used.
Register Duplication or -register_duplication	Use this property to duplicate registers to improve timing. Note This option is available only when Perform Timing-Driven Packing and Placement (-timing) is used.
Combinatorial Logic Optimization or -logic_opt	Use this property to re-synthesize the placed and routed critical paths in the design to improve timing and area, based on the design requirements. Note This option is available only when Perform Timing-Driven Packing and Placement (-timing) is used.
Pack I/O Registers/ Latches into IOBs or -pr	Use this property to reduce setup and clock-to-out timing from pad to register or register to pad.

Advanced Strategies for Improving Performance

Following are advanced strategies for placing and routing your design:

Use SmartXplorer to evaluate different sets of Map and Place and Route properties for your design.
For more information, see Using SmartXplorer.
Floorplan your critical path to help in placement and in packing.
If your design has many Block RAM or DSP blocks, consider floorplanning those components as well. For details, see Floorplanning and Assigning Placement Constraints with PlanAhead Software.
Use clock region area groups with time groups as area groups.
Use this strategy on a limited basis when necessary. This strategy is useful in confining the synchronous elements of global clock buffers to specific clock regions to prevent contention in clock regions between global clocks. For details, see the "AREA_GROUP" and "TIMEGRP" sections in the "Xilinx Constraints" chapter of the Constraints Guide.
Create relationally placed macros (RPMs) to help with packing and placement.
For details, see the "RLOC" section in the "Xilinx Constraints" chapter of the Constraints Guide.
Use SmartPreview™ technology to get an intermediate view of your design after the design has been fully placed and routed but before timing has been fully met.
This strategy allows you to avoid waiting until the design has been fully implemented to perform simulation or analysis, while also allowing the implementation process to continue running to work toward fully meeting the specified timing requirements.
To use this method, right-click the Place & Route process, and select Stop. In the dialog box that appears, select Preserve most recent SmartPreview and continue processing. This creates a temporary .ncd and .twx file, located in the SmartPreview folder in your project directory. You must then view or analyze the files using standalone tools such as Timing Analyzer, FPGA Editor, or BitGen. You can access standalone tools from a command-line outside of Project Navigator. For information on command line tools, see the Command Line Tools User Guide.

Timing Constraints Recommendations

Following are recommendations to reduce runtime and improve design performance using timing constraints:

Do not overconstrain the design to meet timing objectives.
For example, do not place a 120 megahertz (MHz) constraint on a 100 MHz clock. Overconstraining the design makes it more difficult for the placer and router to achieve timing closure. In some cases, this produces worse results than using realistic timing objectives. Overconstraining is the most frequent cause of a long place and route runtime.
Use timing constraints in your synthesis tool to get the best possible design implementation.
Use global timing constraints instead of individual timing constraints where possible.
Use the following Xilinx® constraints where possible:
- TIMEGRP
  Use TIMEGRPs to group signals with the same timing requirements. If a FROM-TO constraint is necessary, define the specific TIMEGRP instead of using generic timing groups, such as FFS and RAMS. This reduces runtime and dramatically reduces memory usage.
- OFFSET
  Use OFFSET constraints with individual timing groups only for exceptions, for example, when the input or output signals are clocked by the same clock but have different timing requirements.
- PERIOD
  Use PERIOD constraints whenever possible. The recommended constraint is TNM_NET. Limit the number of FROM-TO constraints.
- FROM-TO
  Use FROM-TO to define a multi-cycle path that does not require meeting a single cycle. Group as many elements together as possible to limit the number of FROM-TO constraints.
- TIG
  Use TIG constraints when appropriate to reduce the difficulty of meeting all timing constraints during Place and Route.
- LOC
  Use LOC constraints to manually place BlockRAM and Multiplier/DSP design elements to reduce runtime.

Note For detailed information on these constraints, see the "Xilinx Constraints" chapter of the Constraints Guide.