Implementation Strategies using FPGA Editor

ISE

FPGA Editor allows you to view your FPGA and make small modifications to your FPGA design to help improve implementation. FPGA Editor reads the NCD file generated by the Map or Place & Route process, which contains the logic and routing of the design mapped to components, such as CLBs and IOBs. It also reads from and writes to a Physical Constraints File (PCF). The following sections describe implementation strategies using FPGA Editor.

Note For information on launching FPGA Editor from Project Navigator, see Manually Placing and Routing (FPGA Editor) or Viewing and Editing a Routed Design (FPGA Editor). For detailed information on using FPGA Editor, see the FPGA Editor Help.

Implementation Verification

You can use FPGA Editor to view how certain components were configured, such as IOBs, CLBs, or other hard IP, for example, DCMs, MGTs, and BRAMs. For example, you can view the IOBs to see which I/O standard, drive strength, or other configuration options were implemented. You can also edit the CLB to view the LUT equation and see if the flip-flop reset is synchronous or asynchronous or check other configuration options. All of these components can also be edited from within FPGA Editor

In a placed and routed design, you can use FPGA Editor to identify unrouted nets, measure the skew on individual nets, evaluate the proximity of components in a critical path, and make a limited number of manual placement changes to test different placement strategies.

In some cases, the synthesis tool may not compile a module of code as expected. Although simulation is the recommended method for design verification, you can use FPGA Editor as a quick way to check that the design was implemented as expected. For example, if the synthesis tool replicates a Reset net (SR pin) and two registers are not using the same Reset net, Map may not be able to pack the registers into the same slice or IOB. You can check this in FPGA Editor and then modify your synthesis directives to prevent this from occurring.

Manual Placing and Routing

You can use FPGA Editor to fine-tune your design and improve the performance of the Place & Route process. You can manually swap components and pins as well as route and unroute nets. When you manually change the design in FPGA Editor, you must add the new location constraints for the swapped components to the User Constraints File (UCF) or PCF file. This ensures that your changes are retained when the design is re-implemented.

When a group of components requires specific placement, use Relationally Placed Macros (RPMs) to define their relative placement. If you want to maintain both routing and placement, export the directed routing constraints to the UCF file, or use a hard macro. For more information on manual placing and routing, see Placing and Routing Critical Components.

Directed Routing

Directed routing allows the design to retain the routing and timing for a small number of loads and sources. When you use directed routing, the relative position between the sources and loads stay exactly the same. This type of routing is not intended to replace guide. Instead, it allows you to lock specific routing in your design.

Although it is necessary to lock placement so that appropriate routing can be reproduced, do not use directed routing as a placement constraints tool. For example, you can use directed routing to lock the routing for nets, but you should use a predefined macro with specific placement information for all logic that has pins connected to the nets with directed routing constraints.

Note In rare cases, directed routing may block other nets from routing and make the design unroutable. Overuse of directed routing may increase place and route runtimes. If runtimes become too long, use SmartGuide™ technology. For more details, see Using SmartGuide Technology.

Macros

You create macros using multiple design element primitives. Following are the different types of macros:

Hard Macro (.nmc)
When you add a hard macro to your design, you are adding an instance of a library hard macro. Your design can contain multiple instances of the same library hard macro, but each hard macro must have a unique name. You can use FPGA Editor to create hard macros using either of the following methods:
- Save a design as a hard macro. For details, see Saving your Design as a Hard Macro File.
- Create a hard macro. This method is only recommended if you have advanced hand routing skills and knowledge of your targeted architecture. For details, see Creating a New Hard Macro Library File.
Note RPM macros are recommended instead of hard macros wherever possible, because hard macros do not allow timing analysis. A hard macro is seen as a "black box" by the Xilinx® timing tools. Timing can be analyzed to the input and output of the hard macro, but you must manually verify the timing paths within the hard macro.
Relationally Placed Macro (RPM)
RPMs define the spatial relationship of the primitives that comprise the RPM. You can define the relative placements of these primitives to create your own RPMs, using constraints in a UCF file. For details on creating an RPM macro in a UCF file, see the "RLOC" section in the "Xilinx Constraints" chapter of the Constraints Guide. After you create the RPM, you can use FPGA Editor to view the placement of the RPM and to verify that it was created as expected.
Note You can also use FPGA Editor to generate an RPM with directed routes.

Physical Constraints

You can edit the PCF file directly, or you can use the FPGA Editor to modify constraints and then save them to the PCF file when you are satisfied with the constraints. For a list of constraints supported by the FPGA Editor, see the "FPGA Editor" section in the "Entry Strategies for Xilinx Constraints" chapter of the Constraints Guide.

Probes

Use the FPGA Editor Probes command to perform real-time debugging when you want to analyze a few signals at a time. Using the Probes command, you can identify and route internal signals to available I/O pins without rerunning the place and route tools. You can then monitor the real-time signal activity using normal lab test equipment, such as logic and state analyzers or oscilloscopes. For details, see Using Probes.

ChipScope Pro Tool

The ChipScope™ Pro tool assists you in working at the Printed Circuit Board (PCB) level. This software embeds logic analyzer cores into your design, which allow you to view the internal signals and nodes in an FPGA. The ChipScope Pro tool supports user-selectable data channels from 1 to 256. You can change triggers in real time without affecting user logic or having to recompile the design. You can use FPGA Editor to add or remove nets from these cores. For more information on using the ChipScope Pro tool, see ChipScope Pro Tool Debugging Overview and ChipScope Pro Tool Debugging Strategies.