Implementation Overview for CPLDs
After synthesis, you run design implementation, which comprises the
- Translate - merges the incoming netlists
and constraints into a Xilinx® design file.
- Fit - fits the design into the available
resources on the target device.
- Generate Programming File - creates
a programming file that can be downloaded to the device.
The following sections cover how to implement a design and provide
details on each step in the implementation process.
To Implement a Design
- In the Design
panel, select Implementation from the
Design View drop-down list.
- In the Hierarchy pane. select the top module .
- In the Processes pane, do any of the following:
- To run the implementation process in one step, double-click Implement Design. Alternatively, you can select Process > Implement Top Module, as described in Implementing the Top
- To run each of the implementation steps separately, double-click Translate, Fit, or Generate Programming File.
Optionally, you can change the default property values
for the Implement Design process or for the individual implementation
processes. For more information, see Setting Process Properties
The Translate process merges
all of the input netlists and design constraints and outputs a Xilinx Native Generic Database (NGD) file,
which describes the logical design reduced to Xilinx primitives. See
the following table for details. For more information, see Running the Translate Process for
|Command line tool||NGDBuild|
|Tcl command||process run "Translate"|
|Input files||EDIF, SEDIF, EDN, EDF, NGC,
UCF, NCF, URF, NMC|
|Output files||BLD (report), NGD|
|Process properties||Design Properties|
|Tools available after process||PACE, Constraints Editor |
of these tools modifies the User Constraints File (UCF) file. When you rerun Translate with
the updated UCF, the NGD file is updated.
The Fit process performs a logical
design rule check (DRC) on the NGD file produced by the Translate
process. Fit then maps the logic defined by the NGD file into CPLD
elements, such as logic cells, I/O cells, and other components. The
output design is a VM6 file that physically represents the design
fitted to the components in the Xilinx CPLD. See the following table
for details. For more information, see Running the Fit Process
Programming File Generation
Programming File process produces a JEDEC programming file for Xilinx device
configuration. After producing the programming file, you must configure
the device so it can execute the desired function. See the following
table for details. For more information, see Running the Generate
Programming File Process for CPLDs
|Generate Programming File Process|
|Command line tool||Hprep6 |
|Tcl command||process run "Generate
|Output files||JED, ISC|
|Tools available after process||iMPACT |
Additional information is available in
the following Xilinx documentation.
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