ISE
Implementation Overview for CPLDs
After synthesis, you run design implementation, which comprises the following processes:
  1.  Translate - merges the incoming netlists and constraints into a Xilinx® design file.
  2.  Fit - fits the design into the available resources on the target device.
  3.  Generate Programming File - creates a programming file that can be downloaded to the device.
The following sections cover how to implement a design and provide details on each step in the implementation process.
To Implement a Design
  1.  In the Design panel, select Implementation from the Design View drop-down list. Image
  2.  In the Hierarchy pane. select the top module Image.
  3.  In the Processes pane, do any of the following:
    •  To run the implementation process in one step, double-click Implement Design. Alternatively, you can select Process > Implement Top Module, as described in Implementing the Top Module.
    •  To run each of the implementation steps separately, double-click Translate, Fit, or Generate Programming File.
    Note Optionally, you can change the default property values for the Implement Design process or for the individual implementation processes. For more information, see Setting Process Properties.
Translate
The Translate process merges all of the input netlists and design constraints and outputs a Xilinx Native Generic Database (NGD) file, which describes the logical design reduced to Xilinx primitives. See the following table for details. For more information, see Running the Translate Process for CPLDs.
Translate Process
Command line toolNGDBuild
Tcl commandprocess run "Translate"
Input filesEDIF, SEDIF, EDN, EDF, NGC, UCF, NCF, URF, NMC
Output filesBLD (report), NGD
Process propertiesDesign Properties
Tools available after processPACE, Constraints Editor Image
Note  Each of these tools modifies the User Constraints File (UCF) file. When you rerun Translate with the updated UCF, the NGD file is updated.
Fit
The Fit process performs a logical design rule check (DRC) on the NGD file produced by the Translate process. Fit then maps the logic defined by the NGD file into CPLD elements, such as logic cells, I/O cells, and other components. The output design is a VM6 file that physically represents the design fitted to the components in the Xilinx CPLD. See the following table for details. For more information, see Running the Fit Process.
Fit Process
Command line toolCPLDFit
Tcl commandprocess run "Fit"
Input filesNGD
Output filesVM6, RPT (report), HTM (optional report)
Process propertiesFitting Properties, Reports Properties, Simulation Model Properties
Tools available after processTiming Analyzer, XPower Analyzer Image
Programming File Generation
The Generate Programming File process produces a JEDEC programming file for Xilinx device configuration. After producing the programming file, you must configure the device so it can execute the desired function.  See the following table for details. For more information, see Running the Generate Programming File Process for CPLDs.
Generate Programming File Process
Command line toolHprep6
Tcl commandprocess run "Generate Programming File"
Input filesVM6
Output filesJED, ISC
Process propertiesProgramming Properties
Tools available after processiMPACT Image
Additional Resources
Additional information is available in the following Xilinx documentation.
DocumentationTopics Covered
Command Line Tools User GuideCommand line tools, Tcl command information
See Also

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