ISE
Implementation Overview for FPGAs
After synthesis, you run design implementation, which comprises the following steps:
  1.  Translate - merges the incoming netlists and constraints into a Xilinx® design file.
  2.  Map - fits the design into the available resources on the target device, and optionally, places the design.
  3.  Place and Route - places and routes the design to the timing constraints.
  4.  Generate Programming File - creates a bitstream file that can be downloaded to the device.
The following sections cover how to implement a design and provide details on each step in the implementation process.
Note In addition to the standard implementation flow, you can use alternative implementation flows to save runtime and to preserve results. For more information, see Using SmartGuide™ Technology and Partitions Overview. In the Help Viewer, click the Synchronize TOC button Image to view all related Help topics.
To Implement a Design
  1.  In the Design panel, select Implementation from the Design View drop-down list. Image
  2.  In the Hierarchy pane, select the top module Image.
  3.  In the Processes pane, do any of the following:
    •  To run the implementation process in one step, double-click Implement Design. Alternatively, you can select Process > Implement Top Module, as described in Implementing the Top Module.
    •  To run each of the implementation steps separately, double-click Translate, Map, Place & Route, or Generate Programming File.
    Note Optionally, you can change the default property values for the Implement Design process or for the individual implementation processes. For more information, see Setting Process Properties.
Translate
The Translate process merges all of the input netlists and design constraints and outputs a Xilinx Native Generic Database (NGD) file, which describes the logical design reduced to Xilinx primitives. See the following table for details. For more information, see Running the Translate Process for FPGAs.
Translate Process
Command line toolNGDBuild
Tcl commandprocess run "Translate"
Input filesEDIF, SEDIF, EDN, EDF, NGC, UCF, NCF, URF, NMC, BMM
Output filesBLD (report), NGD
Process propertiesTranslate Properties
Tools available after running processConstraints Editor, PlanAhead™ software Image
Note  Each of these tools modifies the User Constraints File (UCF). When you rerun Translate with the updated UCF, the NGD file is updated.
Map
The Map process maps the logic defined by an NGD file into FPGA elements, such as CLBs and IOBs. The output design is a Native Circuit Description (NCD) file that physically represents the design mapped to the components in the Xilinx FPGA. See the following table for details. For more information, see Running the Map Process.
Map Process
Command line toolsMAP
Tcl commandprocess run "Map"
Input filesNGD, NMC, NCD, NGM
Note  The NCD and NGM files are for guiding.
Output filesNCD, PCF, NGM, MRP (report), GRF, MAP, PSR
Process PropertiesMap Properties
Tools available after running processFPGA Editor, PlanAhead software, Timing Analyzer Image
Place and Route
The Place and Route process takes a mapped NCD file, places and routes the design, and produces an NCD file that is used as input for bitstream generation. See the following table for details. For more information, see Running the Place and Route Process.
Place and Route Process
Command line toolsPAR
Tcl commandprocess run "Place & Route"
Input filesNCD, PCF
Note  In addition to the NCD file from MAP, PAR also accepts an NCD file for guiding.
Output filesNCD, PAR (report), PAD, CSV, TXT, GRF, DLY
Process PropertiesPlace & Route Properties
Tools available after running processFPGA Editor, PlanAhead software, Timing Analyzer, TRACE, XPower Analyzer Image
Programming File Generation
The Generate Programming File process produces a bitstream for Xilinx device configuration. After the design is completely routed, you must configure the device so it can execute the desired function. See the following table for details. For more information, see Running the Generate Programming File Process for FPGAs.
Generate Programming File Process
Command line toolsBitGen
Tcl commandprocess run "Generate Programming File"
Input filesNCD, PCF, NKY
Output filesBGN, BIN, BIT, DRC, ISC, LL, MSD, MSK, NKY, ISC, RBA, RBB, RBD, RBT
Process PropertiesGeneral Options, Configuration Options, Startup Options, Readback Options, Encryption Options
Tools available after running processiMPACT Image
Additional Resources
Additional information is available in the following Xilinx documentation.
DocumentationTopics Covered
Command Line Tools User GuideCommand line tools, Tcl command information
See Also

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