ISE
Implementation Analysis Overview
After implementing your design, you can use the following methods
to analyze your implementation results:
- Review reports, as described in the Design Summary Overview.
- Analyze power consumption, as described in the Power Analysis Overview.
For FPGA designs, you can also do the following:
- Analyze reports, as described in the Report Analysis Overview.
- Analyze timing, as described in the Timing Analysis Overview.
- Analyze implementation results, as described in Exploring Implementation Results with PlanAhead™ Software
Additional Resources
Additional information is available
in the following Xilinx® documentation.
| Documentation | Topics Covered |
|---|---|
| Command Line Tools User Guide | Translate, MAP, PAR, CPLDFit, and XPower command line tools |
| PlanAhead User Guide | PlanAhead software (FPGAs) |
| Timing Analyzer Help Note In the Help Viewer,
click the Synchronize TOC button  to view all related Help topics. | Timing Analyzer software (FPGAs) |
| Timing Analyzer Help for CPLDs | Timing Analyzer software (CPLDs) |
| XPower Analyzer Help Note In the Help Viewer,
click the Synchronize TOC button to view all related Help topics. | XPower Analyzer software |
© Copyright 1995–2009, Xilinx®
Inc. All rights reserved.