ChipScope Pro Tool Debugging Overview

ISE

After configuring your device, you can debug your FPGA design using the Xilinx® ChipScope™ Pro tool. The ChipScope Pro tool comprises the ChipScope Pro cores in the CORE Generator™ software, the ChipScope Pro Core Inserter, and the ChipScope Pro Analyzer. To use this process, you must purchase the ChipScope Pro tool and must design with debug and verification in mind, as described in the following sections.

Note For more information on the ChipScope Pro tool, see the ChipScope Pro Tool Web page. For more information on using the ChipScope Pro tool, see the ChipScope Pro Tool Documentation.

To Launch the ChipScope Pro Tool from Project Navigator

In the Design panel, select Implementation from the Design View drop-down list.
In the Hierarchy pane, select the top module .
In the Processes pane, double-click Analyze Design Using ChipScope.

ChipScope Pro Tool Design Flow

To use the ChipScope Pro tool to perform in-circuit verification, you must do the following:

Insert ChipScope Pro cores in your design using the CORE Generator software or ChipScope Pro Core Inserter.
In Project Navigator, implement your design in and configure your device.
In the ChipScope Pro Analyzer, analyze your design.

ChipScope Pro Cores

The ChipScope Pro tool allows you to embed the following cores within your design, which assist with on-chip debugging: integrated logic analyzer (ILA), integrated bus analyzer (IBA), and virtual input/output (VIO) low-profile software cores. These cores allow you to view internal signals and nodes in your FPGA, including the IBM CoreConnect processor local bus (PLB) that supports the IBM PowerPC® 405 processor. Following are the ChipScope Pro cores and their functions:

ICON
The Integrated Controller (ICON) core provides the communication between the embedded ILA, IBA, and VIO cores and the computer running the ChipScope Pro Analyzer software.
ILA
The ILA core is a customizable logic analyzer core that can be used to monitor the internal signals in your design. Because the ILA core is synchronous to the design being monitored, all design clock constraints applied to your design are also applied to the components inside the ILA core.
ATC2
The Agilent Trace Core 2 (ATC2) is a customizable logic analyzer core, which is similar to the ILA core but does not use on-chip Block RAM resources to store captured trace data. The ATC2 core synchronizes ChipScope Pro to the Agilent FPGA dynamic probe technology, delivering the first integrated application for FPGA debug with logic analyzers.
VIO
The virtual input/output core is a customizable core that can both monitor and drive internal FPGA signals in real time. Unlike the ILA and IBA cores, the VIO core does not require on-chip RAM.

Note EDK provides additional specific cores. For more information, refer to the "Configuring PLB IBA ChipScope Cores" topic in the XPS Help in EDK.

ChipScope Pro Core Insertion

You can insert ChipScope Pro cores in your design with the ChipScope Pro tool using one of the following methods:

During design entry using the CORE Generator software
Use the CORE Generator software to create the cores and instantiate them in your HDL source file. Use this software to generate all of the cores available in the ChipScope Pro tool. You can use the wizard provided to create NGC netlists with HDL instantiation templates for any of the supported synthesis tools. You can then use the templates to connect the ChipScope Pro cores to the design logic that you want to view.
After the Synthesize process in ChipScope Pro Core Inserter
Use the ChipScope Pro Core Inserter to create the ILA, ATC2, and ICON cores and insert them in a post-synthesis netlist. For detailed information on inserting cores, see Running the ChipScope Pro Core Inserter.

The following table shows the advantages and disadvantages for each method.

CORE Generator Software	ChipScope Pro Core Inserter
- Core generation and insertion are separate steps	+ Core generation and insertion are one step
+ Standard implementation flow	- Core Inserter performs part of the Translate process
- HDL code must be modified	+ HDL code does not require modification
+ Every node is available for debug	- Only post-synthesis nodes are available for debug
- To exclude cores, comment them out of the HDL code	+ To exclude cores, remove the CDC file in Project Navigator
+ VIO cores are easily inserted	- VIO cores are not available

Design Implementation

When using ChipScope Pro cores, you implement your design as usual. For information on implementation, see Implementation Overview for FPGAs.

Design Analysis

The ChipScope Pro Analyzer tool interfaces directly to the ChipScope Pro cores. Use this software to download designs, set trigger conditions, and display data. You can show data as waveforms, lists, or graphs, and can tokenize values. For detailed information on analyzing the cores, see the ChipScope Pro Tool Documentation.

Additional Resources

Additional information is available in the following Xilinx documentation.

Documentation	Topics Covered
ChipScope Pro Tool Documentation	ChipScope Pro tool