ISE
Simulation Overview
During HDL simulation, the simulator
software verifies the functionality and timing of your design or portion
of your design. The simulator interprets VHDL or Verilog code into
circuit functionality and displays logical results of the described
HDL to determine correct circuit operation. Simulation allows you
to create and verify complex functions in a relatively small amount
of time.
Simulation takes place at several points in the design flow. It
is one of the first steps after design entry and one of the last steps
after implementation, as part of verifying the end functionality and
performance of the design. Simulation is an iterative process, which
may require repeating until both design functionality and timing is
met. For a typical design, simulation comprises the following high-level
steps:
- Compilation of the simulation libraries
Note Library compilation is not necessary when using the ISim simulator. - Creation of the design and test bench
- Functional simulation
- Implementation of the design and creation of the timing simulation
netlist
- Timing simulation
Additional Resources
Additional information is available
in the following Xilinx® documentation.
| Documentation | Topics Covered |
|---|---|
| Synthesis and Simulation Design Guide | Xilinx simulation capabilities |
| ISim Help Note In the Help Viewer,
click the Synchronize TOC button  to view all related Help topics. | Xilinx ISim simulator |
| Libraries Guides | Xilinx Unified Library Symbols |
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