ISE
Timing Simulation
After you implement the design using the ISE® software, you can perform timing simulation on the design. Timing simulation is the closest emulation to actually downloading a design to a device. It allows you to check that the implemented design meets all functional and timing requirements and behaves as you expect in the device. Performing a thorough timing simulation ensures that the finished design is free of defects that can easily be missed, such as the following:
  •  Post-synthesis and implementation functionality changes caused by the following:
    •  Synthesis attributes or constraints that can cause simulation/implementation mismatches, such as translate_off/translate_on or full_case/parallel case.
    •  UNISIM attributes applied in the UCF file or using synthesis attributes
    •  Differences between synthesis interpretation of language in different simulators
  •  Dual-port RAM collisions
  •  Missing or improperly applied timing constraints
  •  Operation of asynchronous paths
When working with FPGAs, you can perform timing simulation in conjunction with in-system testing to help you further understand how the device is operating. For more information, see the ChipScope™ Pro Tool Debugging Overview.
Note For detailed information on Xilinx® timing simulation, see the Synthesis and Simulation Design Guide.
Timing Simulation Steps
To perform a full timing simulation, the design must be placed and routed. Following are the general steps in a full timing simulation:
  1.  Ensure that your libraries are properly compiled and mapped.
    Ensure that the SIMPRIM library is properly compiled and mapped to the simulator. If you are using the ISim or the ModelSim Xilinx Edition simulator, this is automatically done for you. For details, see Simulation Libraries.
  2.  The netlister generates a structural simulation netlist, based on the models for the device primitives in the design, and an associated Standard Delay Format (SDF) file that contains all of the annotated delays for the design for use during simulation.
    If you are using Project Navigator, run the Simulate Post-Place and Route Model (FPGAs), as described in Performing Post-Place & Route Simulation, or Simulate Post-Fit Model (CPLDs) process to generate the netlist, as described in Performing Post-Fit Simulation.
    If you are running from the command line, use NetGen to create the netlist files. For information on using NetGen, see the Command Line Tools User Guide or the Synthesis and Simulation Design Guide.  
  3.  Load the SDF file.
    The instructions for loading the SDF file differ depending on the simulator. Please refer to the simulator documentation. If you are using ISim, see the ISim Help. In the Help Viewer, click the Synchronize TOC button Image to view all related Help topics.
  4.  Use the structural timing netlist, SDF file, and test bench to perform a timing simulation.
    Timing simulation is similar to functional simulation, except that you are viewing a structural implementation of the design. In addition, you must account for the timing delays in the design. When you invoke the simulator from within the Project Navigator, the ISE tools automatically run these steps. For more information, see the following topics:
    If you are running the simulator outside of the Project Navigator environment, refer to the documentation for your simulator.
See Also
Simulation Overview

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