ISE
Timing Analysis Overview
After running the Implement
Design process, you can use Timing Analyzer to perform a detailed analysis
of your FPGA design. This ensures that the specified timing constraints
were properly passed to the implementation tools. Performing a detailed
analysis includes the following:
- Verify that timing requirements were met for all paths in your design.
- Analyze setup and hold performance for all constrained paths in the design.
- Verify that operational frequencies are within component performance limits.
- Analyze unconstrained paths to determine if any critical timing paths have been left unconstrained.
To efficiently analyze timing, a top-down method is recommended,
which begins with an inspection of the overall performance of the
design, followed by an inspection of the different categories of constraints,
a single constraint, and finally, a specific path in the design. After
analysis is complete, a detailed report of that analysis is created,
which can be customized to include only the information you need.
You can use the Timing Analyzer to perform a detailed analysis of your
FPGA design as follows:
You can launch the Timing Analyzer from the Project Navigator using either
of the following processes. Alternatively, you can launch the Timing Analyzer using
the Tools menu commands.
Additional Resources
Additional information is available
in the following Xilinx® documentation.
| Documentation | Topics Covered |
|---|---|
| Constraints Guide | Constraint types, entry methods supported for each constraint, and a listing of all constraints |
| Timing Analyzer Help Note In the Help Viewer,
click the Synchronize TOC button  to view all related Help topics. | Timing Analyzer software |