ISE
Working with CORE Generator IP
You can create CORE Generator™ IP to instantiate in your HDL or schematic designs. When you create IP, the CORE Generator software produces a combination of the following files and places them in the specified directory for use in your ISE® project:
  •  XCO - This file contains core options and parameters.
  •  EDN/NGC - This is the implementation netlist for the IP cores which output netlists. It is passed on to the Translate (NGDBuild) process.
  •  SYM - This schematic symbol is automatically generated for instantiating the IP in a schematic.
  •  VHO or VEO template files - These files are automatically generated for instantiating the IP in an HDL file.
  •  VHD or V simulation wrapper files - These files are provided for simulation of IP cores which output netlists.
  •  VHD or V source-code files - These files are the actual source-code required for both synthesis and simulation of IP cores which output source-code.
  •  XISE, ISE, and GISE project files - These files are used to help track and manage the core in the context of the ISE project. You should not need to interact directly with these files.
By default, when you create a new CORE Generator core, the core files are placed in a subdirectory of the main project directory called ipcore_dir. If necessary, you can specify a different location in the New Source Wizard when you create the core.
Note For details on using the CORE Generator software, see the CORE Generator Help. In the Help Viewer, click the Synchronize TOC button Image to view all related Help topics.
To Create CORE Generator IP
  1.  Create your IP as described in Creating a Source File, selecting IP as your source type.
    Note   In the New Source Wizard, CORE Generator IP and Architecture Wizard IP are grouped together. CORE Generator IP is represented by the light bulb icon Image.
  2.  After you click Finish, an IP core customization tool appears in which you can define your IP.
  3.  After you customize and generate the IP, the XCO file is added to your project and appears in the Hierarchy pane of the Design panel.
Note If you are creating the IP outside of Project Navigator, you must specify your output files in the CORE Generator software, as described in Specifying the Output Files.
To Add CORE Generator IP to a Project
If you have an existing CORE Generator IP core (XCO file) that you want to add to your project, you can add it as described in Adding a Source File to a Project. The XCO source file must be added to the project to be properly compiled into the design during synthesis and implementation.
Note If you generated your source file using the New Source Wizard and selected Add to Project, you do not need to add the source file to your project; it is automatically added to your project.
To Instantiate CORE Generator IP in an HDL File
When you create IP, the CORE Generator software automatically generates a VHDL or Verilog instantiation template file that you can use to instantiate the IP into your HDL design. To view and use the instantiation template, see Creating and Viewing an HDL Instantiation Template.
Note You must modify the signal names in your HDL file to map the core correctly into your design. For more information on working with HDL files, see the HDL Overview.
To Instantiate CORE Generator IP in a Schematic
When you create IP, the CORE Generator software automatically generates a schematic symbol and adds it to the local symbol library for your project. To instantiate IP in your schematic, see Adding a Symbol Instance.
Note For more information on working with schematics, see the Schematic Overview.
To Edit CORE Generator IP
After the IP is created and added to the project, you can edit it as described in Editing a Source File.
Note For information on managing CORE Generator IP in the project, including how to regenerate cores for new device architectures and new software versions, see Managing Cores.
To Simulate CORE Generator IP in a Design
To simulate a design that includes CORE Generator IP, pull the XilinxCoreLib library into your simulator Workspace. For details, see Simulation Libraries.
See Also

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