Timing constraints are typically specified globally but can also be specified for individual paths. Global constraints include period constraints for each clock (PERIOD), setup times for each input (OFFSET_IN), and clock-to-out constraints for each output (OFFSET_OUT). You can enter timing constraints using the Create Timing Constraints process in Project Navigator. This creates a text-based User Constraints File (UCF), which is used during implementation. You can enter timing constraints for synthesis in a separate XST Constraint File (XCF). For more information on entering constraints, see Constraints Entry Methods.

Results for the timing constraints are automatically reported after implementation, and are also available from the Design Summary. To analyze the results of your timing specifications, use Timing Analyzer or the command line tools Timing Reporter and Circuit Evaluator (TRACE) for FPGA designs and TAEngine for CPLD designs.

For FPGA designs, you can specify placement constraints for each type of logic element, such as BRAMs, DSPs, LUTs, FFs, I/Os, IOBs, and global buffers. Individual logic gates, such as AND and OR gates, are mapped into CLB function generators before the constraints are read and cannot be constrained. For CPLD designs, you can specify placement constraints for macrocells, for function blocks, and for I/Os.

Synthesis constraints instruct the synthesis tool to perform specific operations. When using XST for synthesis, synthesis constraints control how XST processes and implements FPGA resources, such as state machines (FSM_EXTRACT, FSM_ENCODING), multiplexers (MUX_EXTRACT), and multipliers (MULT_STYLE), during the HDL synthesis and low level optimization steps. Synthesis constraints also allow control of register duplication (REGISTER_DUPLICATION) and fanout control (MAX_FANOUT) during global timing optimization. To give XST specific targets during global optimization, you can enter timing constraints for synthesis in the XCF file.