Using the Design Views

ISE

The Design View (“Sources for”) area in the Project Navigator Design panel allows you to view your design based on the different phases in the ISE® design flow. When you select a Design View, all the source files associated with that phase appear in the Hierarchy pane. When you select a source file in the Hierarchy pane, the processes associated with that source file appear in the Processes pane. The following Design Views are available.

Some source files are associated with one Design View only and some are associated with multiple Design Views. When you add a source file to the project, the Adding Source Files dialog box allows you to associate the source file with a Design View. For details, see Adding a Source File to a Project.

Note You can change the Design View association after the source file has been added, as described in Changing Source Properties.

Implementation View

The Implementation view shows source files that apply to synthesis and implementation. When you select a file in the Hierarchy pane, only processes related to synthesis or implementation appear in the Processes pane. Simulation processes are not available.

Note For more information on synthesis, see XST Synthesis Overview. For more information on implementation, see Implementation Overview for FPGAs or Implementation Overview for CPLDs.

Behavioral Simulation View

The Behavioral Simulation view shows sources files that apply to behavioral simulation, which may include any of the following:

HDL test benches
HDL source files used for both synthesis and behavioral simulation
Simulation-only HDL source files, such as IP simulation models or external simulation models

Simulation netlists generated for post-implementation simulation are not displayed in this view.

Note The available Simulation views vary based on the simulation tool you are using. For example, only the Behavioral Simulation and Post-Route Simulation views are available for ISim.

Post-Translate, Post-Map, Post-Route, and Post-Fit Simulation Views

The Post-Translate, Post-Map, Post-Route, and Post-Fit Simulation views show source files and simulation netlists that apply to simulation after the design is implemented. Source files may include any of the following:

HDL test benches
Simulation-only HDL source files, such as IP simulation models or external simulation models
Structural HDL simulation netlists generated after the design is implemented

After simulation model netlists are generated during the implementation process, they are automatically displayed in the appropriate Post-* Simulation view, if there is a module or test bench that instantiates them. For information on generating simulation models during the implementation process, see the following topics:

To simulate a lower-level module of your design, you can select the Generate Multiple Hierarchical Netlist property in the Process Properties dialog box for the appropriate Generate Post-* Simulation Model process, as described in Setting Process Properties. After the simulation model netlist is generated, you can view the netlist in the Simulation view. The netlist appears in the Hierarchy pane under the test bench that instantiates it. To simulate the lower-level module, select the test bench in the Hierarchy pane, and run simulation from the Processes pane.

Simulation Source Files

When adding a source file to the project that only applies to simulation, select the Simulation option in the Adding Source Files dialog box, as described in Adding a Source File to a Project. Following are examples of simulation-only source files:

Test Benches
The Simulation views show test benches with the module they instantiate underneath the test bench in the hierarchy. You can add hierarchical test benches (that is, test benches that instantiate other test benches), and the test benches appear correctly in the Simulation view hierarchy (that is, the instantiated test bench appears underneath the main test bench in the hierarchy).
You can add multiple test benches to the project. All source files associated using the Simulation option appear across all Simulation views. To simulate a test bench, select the test bench in the appropriate Simulation view, and run the simulation process in the Processes pane.
When you add a test bench to the project, you must ensure that the associated Design View is set to a Simulation view. For simulation source files, Project Navigator automatically selects the Design View association based on the file name. Project Navigator uses a predefined set of patterns to determine whether the file is a Simulation source file and whether the file is a test bench. These patterns are defined in the data file $Xilinx/data/projnav/xil_tb_patterns.txt. If the source file name matches any of these regular expression patterns, the Design View association is automatically set to a Simulation view when you add a file to the project. After the file is added to the project, you can change the default association in the Source Properties dialog box, as described in Changing Source Properties.
Note To modify the list of patterns that Project Navigator uses to detect test bench source files, you can edit the $Xilinx/data/projnav/xil_tb_patterns.txt data file. You can either edit the file in the installation location, or you can create a copy of the file and place it in the project directory. The file in the project directory overrides the file in the installation area.
HDL
The Simulation view shows test benches with the HDL simulation model they instantiate underneath the test bench in the hierarchy. For test benches that instantiate an external simulation model, the simulation model is compiled and sent to the simulator when the test bench is simulated.

Note For more information on simulation, see Simulation Overview.