Project Navigator allows
you to manage your FPGA and CPLD designs using an ISE® project,
which contains all the source files and settings specific to your
design. First, you must create a project and then, add source files,
and set process properties. After you create a project, you can run
processes to implement, constrain, and analyze your design. Project Navigator provides
a wizard to help you create a project as follows.
Note If you
prefer, you can create a project using the
New Project dialog box instead of the New Project Wizard. This dialog box creates a new
project without adding source files. To use the New Project dialog
box, deselect the
Use new project wizard option
in the
ISE General
page of the Preferences dialog box.

To Create a Project
- Select File > New Project to launch
the New Project Wizard.
- Set the options in the Create New Project
page, and click Next.
- Set the options in the Device Properties
page, and click Next.
Note If you are working with an EDIF or NGC/NGO project, you must set options in the
Import
EDIF/NGC Project page prior to this step, and skip to step
6 after completing this step.
- Optionally, create the top-level source file for your project
in the Create New Source page, and click Next.
Note You can only create one new source file while creating a new
project. You can create additional new sources after your project
is created.

- Optionally, add existing source files to your project in
the Add Existing Sources page, and click Next.
- Review the Project Summary
page, and click Finish to create the
project.
Project Navigator creates the project file,
project_name.xise, in the directory you specified.
All source files added to the project appear in the Hierarchy pane
of the
Design panel. Project Navigator manages your project based on the design properties
(top-level module type, device type, synthesis tool, and language)
you selected when you created the project. It organizes all the parts
of your design and keeps track of the processes necessary to move
the design from design entry through implementation to programming
the targeted Xilinx® device.
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