ISE
Running the Translate Process for FPGAs
Translate is the first step in the implementation process. The Translate process merges all of the input netlists and design constraint information and outputs a Xilinx® Native Generic Database (NGD) file. The output NGD file can then be mapped to the targeted device family.
Note For an overview of the Translate process, see the Implementation Overview for FPGAs. For detailed information about Translate, see the “NGDBuild” chapter of the Command Line Tools User Guide.
To Run the Translate Process
  1.  In the Design panel, select Implementation from the Design View drop-down list. Image
  2.  In the Hierarchy pane, select the top module Image.
  3.  Optional. In the Processes pane, expand the Implement Design process, right-click Translate, and select Process Properties to set the Translate Properties.
  4.  Double-click the Translate process.
All processes necessary to successfully complete the Translate process are run automatically. The Translate process generates an NGD file.
After running Translate, you can do any of the following:
  •  View the Translation report. Image
  •  Generate a post-translate simulation model. Image
  •  Perform post-translate functional simulation. Image
  •  Update timing constraints in the Xilinx Constraints Editor. Image
  •  Assign package pins. Image
  •  Run the Map process. Image

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