ISE
Using Precision Software for Synthesis
You can use the Precision RTL Synthesis software from Mentor Graphics, Inc., to maximize the performance of CPLDs and FPGAs as well as next-generation, multi-million gate field programmable system-on-chip (FPSoC) devices. Precision RTL Synthesis is a comprehensive software suite in which you can perform VHDL and Verilog entry, advanced register transfer level logic synthesis, constraint-based optimization, state-of-the-art timing analysis, schematic viewing, and encapsulated place and route.
For detailed information about the Precision software, including how to get the best results, please refer to the Precision documentation. You can access the documentation from the standalone Precision RTL Synthesis software or from the Mentor Graphics website at http://www.mentor.com.
The ISE® software works with the latest Precision software. When invoked from the ISE software, the Precision software runs in batch mode for both floating and node-locked licenses. If you run the Precision software in standalone mode, any changes that you make to your project are not imported back into your ISE project.
Note Precision RTL Synthesis tools are not provided with the ISE software. These tools are available from Mentor Graphics, Inc. Xilinx® provides integration with the Precision RTL Synthesis software when both ISE software and Precision RTL Synthesis software are installed. If you installed a synthesis tool but it does not appear as an option, set the path to the synthesis software in the Integrated Tools Options page of the Preferences dialog box. Image
To Use Precision Software for Synthesis
  1.  In Project Navigator, do one of the following:
  2.  In the Design panel, select Implementation from the Design View drop-down list. Image
  3.  In the Hierarchy pane, select the top module Image.
  4.  Optional. Default property values are used for the Synthesize process unless you modify them. You can set the Precision Synthesis Options in the Process Properties dialog box. Image
  5.  In the Processes pane, double-click Synthesize - Precision. You can also double-click any of the following Precision processes to debug and synthesize your design:
    •  Check Syntax
      This process checks the selected design source files for syntax errors in your HDL code and checks the coverage of your RTL synthesis constraints.
    •  View Log File
      This process shows the log file from the most recent Synthesize or Check Syntax process.
    •  View RTL Schematic
      This process shows the RTL schematic from the most recent Synthesize or Check Syntax process. If a schematic does not exist, the Check Syntax process is launched to produce an RTL schematic.
    •  View Technology Schematic
      This process shows the technology schematic from the most recent Synthesize process. If a schematic does not exist, the Synthesize process is launched to produce a technology schematic.
    •  View Critical Path Schematic
      This process shows the critical path schematic from the most recent Synthesize process. If a schematic does not exist, the Synthesize process is launched to produce a technology schematic.
      Note If no timing constraints are set, you cannot run this process.
    •  Open Standalone Precision Project
      This process launches the Precision Synthesis software in standalone mode and generates a project based on the input files used for the Project Navigator project. You can run all of the Precision Synthesis processes listed above in standalone mode.
      Note After opening your Precision project in standalone mode, any changes that you make to your project are not imported back into your ISE project. If you want ISE to use any generated results from your standalone session, you must run the file: save_to_ise.tcl. This file is located in your Precision project directory and copies the Precision EDF, UCF, and report output files into your ISE project directory.
The Precision tools run the Synthesize process and all preceding processes. The resulting EDIF file is placed in your project directory.
After synthesis, you can run the Implement Design process. Image

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