Xilinx® ISim is a Hardware Description Language (HDL) simulator that enables you to
perform functional and timing simulations for VHDL, Verilog and mixed
VHDL/Verilog designs.
Simulation Libraries
The Xilinx simulation
device libraries are precompiled, and are updated automatically when
updates are installed. Do not run the Simulation Library Compilation Wizard (Compxlib) to compile libraries
for use with ISim.
Language Support
ISim supports the
following languages.
| Language | Support |
|---|
| VHDL | IEEE-STD-1076-2000 |
| Verilog | IEEE-STD-1364-2001 |
| SDF | Xilinx [NetGen] generated
SDF Files |
| VITAL | VITAL-2000 |
| Mixed VHDL/Verilog | Yes |
| VHDL FLI/VHPI | No |
| Verilog PLI | No |
| SystemVerilog | No |
| Other Assertion-Based Languages | No |
Feature Support
ISim supports the
following features.
| Feature | Support |
|---|
| Incremental Compilation | Yes |
| Source Code Debugging | Yes |
| SDF Annotation | Yes |
| VCD Generation | Yes |
| SAIF Support | Yes |
| Hard IP - MGT, PPC, PCIe®,
etc | Yes |
| Multi-threading | Yes |
© Copyright 1995–2009, Xilinx®
Inc. All rights reserved.