ISim
fuse Options
The fuse command options are as follows.
-d <macro_definition> [ = <value> ]This option is for Verilog only. Define the macros used in Verilog files, and any value they require. More than one -d can be specified.
Note There should be no space between the "=" and the value as this space would be interpreted as part of the value.
-f <cmd_file>You can save fuse command options in a text file for future use. This option reads and executes the saved options, specified in cmd_file.
-generic_top "<parameter>=<value>"Overrides generic or parameter of a top level design unit with the specified value. For example, -generic_top “P=10” would apply the value of 10 on top level parameter P before elaboration.
-hDisplays all command line options and their usage.  
-i <include_path>This option is for Verilog only. Specifies that if fuse calls vlogcomp, it should use the specified path for Verilog ’include directives. Each -i can be used for only one include path. More than one -i can be specified.  Place quotes around paths with spaces.
-incrementalCompiles only the files that have changed since last compile.  
-initfile <sim_init_file>Specifies a user defined simulator init file to add to or to override the logical-to-physical mappings of libraries provided by the default xilinxsim.ini file.
-intstyle
ise | xflow | silent
Use one of the specified styles for printing messages. Specify ise to print messages for the ISE Console or xflow to print messages for XFLOW. Specify silent to suppress all messages.  By default all messages are printed.  
-ise <file>Enables you to specify a Xilinx ISE file.
-L|-lib <search_lib> [ = <lib_path> ] Specifies other libraries and optionally the physical path name for those libraries. Multiple -L can be used, and are treated as resource libraries. The physical path provided through -L overrides mappings provided by the xilinxsim.ini file.
Search_lib is the logical name of the specified library optionally followed by the lib_path, the path to the physical library. For example:
-L mylib=C:home/mylib
For Verilog designs, fuse searches for libraries in the order that the -L options are coded. For example:
fuse -L unisim -L abcsim -L xyzsim mytop
First, fuse searches for design units in UNISIM, and then abcsim,  and xyzsim. If a design unit was defined in abcsim as well as in xyzsim, the one in abcsim would be used as that appears before xyzsim.
If the order was changed to:
fuse -L unisim -L xyzsim -L abcsim mytop
And both xyzsim and abcsim defined the same design unit, fuse would pick the design unit from xyzsim.
-maxdelayThis option is for Verilog only. Specifies that if fuse calls vlogcomp, it should use worst case delays.  
-maxdesigndepth <depth>Overrides maximum design depth allowed by the elaborator. If a design exceeds the depth, elaborator would error out. May be used to increase the depth in case the elaborator falsely thinks that a design has infinite recursive instantiation.
-mindelayThis option is for Verilog only. Specifies that if fuse calls vlogcomp, it should use fastest possible delays.  
-mt <value>Specifies the number of sub-compilation jobs which can be run in parallel. Possible values are on, off, or an integer greater than 1. Default is on, where the compiler automatically chooses a number based on number of cores in the system.
-nodebugGenerates output that has no information for debugging your HDL code during simulation. Output with no debug information runs simulation faster. The default is to generate HDL units for debugging.
-nospecifyThis option is for Verilog only. Disables specify block functionality.
-notimingchecksThis option is for Verilog only. Disables the timing checks.
-o <sim_exe> Specifies the name of the simulation executable output file. The name of the file is sim_exe. If you do not use this option, the default executable name is:
work_lib/mod_name/platform/x.exe
where:
  •  work_lib is the work library.
  •  mod_name is the first top module specified.
  •  platform is Windows.
-override_timeprecisionOverrides the time precision (unit of accuracy) of all Verilog modules in the design with the time precision specified in the -timescale option.
-override_timeunitOverrides the time unit (unit of measurement of delays) of all Verilog modules in the design with the time unit specified in the -timescale option.
-prj <prj_file>.prjSpecifies a project file to use for input.  A project file contains a list of all the files associated with a design. It is the main source file used by the ISE® software.
Prj_file is the project file and must have a prj extension.
-rangecheckThis option is for VHDL only. Specifies value range check to be performed on VHDL assignments.
Note This option does not affect index range checking for arrays. ISim always checks an index into an array for being within the allowed range.
By default -rangecheck it is turned off.
-sourcelibdirSpecifies the source directory for library modules. For more information and examples, see Supporting Source Libraries.
-sourcelibextSpecifies the file extension for source files for modules. The –sourcelibdir option provides the location for these files. For more information and examples, see Supporting Source Libraries.
-sourcelibfileSpecifies the filename for library modules. For more information and examples, see Supporting Source Libraries.
-timeprecision_vhdl<time_precision>Specifies the time precision (unit of accuracy) for all VHDL design units.
The time_precision is entered as number (1|10|100|...) followed by unit (fs|ps|ns|us|ms|s).
The default is 1ps.
-timescale <time_unit/time_precision>Specifies the default timescale for Verilog modules that do not have an effective timescale. The time_unit is the unit of measurement of delays. The time_precision is the unit of accuracy.
Both time_unit and time_precision are entered as number (1|10|100|...) followed by unit (fs|ps|ns|us|ms|s).
The default timescale is 1ns/1ps.
-typdelayThis option is for Verilog only. Specifies that if fuse calls vlogcomp, it should use typical delays.  
-v <value>Specifies the verbosity level for printing messages. Allowed values are 0, 1, or 2. The default is 0.
fuse -v 1 prints useful debugging information, which can help to identify problems in ISim compilers.
  •  Dumps the library mapping as seen by ISim compiler after reading all available library mapping files (xilinxsim.ini)
  •  Gets verbose messages from design elaborator
  •  Gets the dumps of current values of environment variables which affect the behavior of the ISim compiler
  •  Gets the list of loaded shared objects by the ISim compiler
  •  Dumps operating system information, including version number and processor
  •  Dumps path to GCC compiler being used to compile the generated code
-versionPrints the compiler version.

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