a simulation model is created for a system, the software data must
be included in the memory simulation models for the system to run
A C program that has been compiled to generate an executable file
can be put inside the simulation models. When running and debugging
the software program in the simulator, there will be several iterations
of changes and compilation only of the C program and not the hardware
design. Creating this data inside the simulation models would be inefficient.
If there are no hardware changes, there is no need to run any hardware
creation or implementation tools again.
Xilinx® EDK supports initialization of data in block RAM blocks.
Block RAM blocks are formed of several block RAMs arranged and configured
to create a memory of the size specified in the design. The simulation
models that Xilinx provides for these block RAMs use generics in the
case of VHDL and parameters in the case of Verilog as the means to
initialize them with data.
If there is any program with which to initialize memory, EDK creates
separate memory initialization Hardware Description Language (HDL) files that include
the data for the design.
For VHDL simulation models, EDK generates a VHDL file that contains
a configuration for the system with all initialization values. For
a design described in a file called system.mhs, there is a VHDL system configuration in the file system_init.vhd. The configuration in this file maps the required generics for each
of the block RAM blocks connected to a processor in the system.
For Verilog simulation models, EDK generates a Verilog file that
contains an extra module to be used along with the system with all
initialization values. For a design described in a file called system.mhs, there is a VHDL system configuration in the
file system_init.v. This module does not have
any ports and does not instantiate any other module. It only contains
a set of defparam statements to define the required parameters for
each of the block RAM blocks connected to a processor in the system.