ISE
New Project Dialog Box
Use this dialog box to create a new project, as described in Creating a Project. To access this dialog box, select File > New Project.
Note This dialog box appears when the New Project Wizard option is disabled in the ISE® General page of the Preferences dialog box.
  •  Name
    Specifies the name for the project. Follow the naming conventions in Naming Conventions.
  •  Location
    Specifies the location of the project. You can browse to a directory or enter the name of a directory. If you enter the name of a directory that does not exist, Project Navigator creates the directory. By default, the software automatically creates a subdirectory based on the name entered in the Name field.
    Note It is recommended that you store only one project per directory. If multiple projects share the same directory, file conflicts can occur.
  •  Working Directory
    Specifies the location of the working directory. By default, the working directory is the same as the project directory. However, you can specify a working directory if you want to keep your ISE project file (.xise extension) separate from your working area.
  •  Description
    Allows you to add a description for your project. This field is optional.
  •  Product Category
    Specifies an applicable product category. This selection filters the device families and devices that are available in the Family and Device fields.
  •  Family
    Specifies the device family, or Xilinx® architecture, into which you will implement your design.
  •  Device
    Specifies the device into which you will implement your design.
  •  Package
    Specifies the package for the device being targeted.
  •  Speed
    Specifies the speed grade of the device being targeted.
  •  Top-Level Source Type
    Specifies the source type for the top-level design.
    •  HDL
      Select this option if your top-level design file is a VHDL or Verilog file. An HDL Project can include lower-level modules of different file types, such as other HDL files, schematics, and "black boxes," such as IP cores and EDIF files.
    •  Schematic
      Select this option if your top-level design file is a schematic file. A schematic project can include lower-level modules of different file types, such as HDL files, other schematics, and "black boxes," such as IP cores and EDIF files. Project Navigator automatically converts any schematic files in your design to structural HDL before implementation; therefore, you must specify a synthesis tool when working with schematic projects.
    •  EDIF
      Select this option if you want to use an EDIF netlist as the top-level source for the project. This may be the case if you are using a synthesis tool outside of Project Navigator to synthesize the design.
    •  NGC/NGO
      Select this option if you want to use an NGC or NGO netlist as the top-level source for the project.
  •  Synthesis Tool
    Specifies the synthesis tool and synthesis language used for your design. For synthesis tools that support only single-language designs, select the appropriate language for your design (for example, Synplify (VHDL) or Synplify (Verilog)).
    •  XST
      Xilinx Synthesis Technology (XST) is provided with the ISE® software. It supports projects that include VHDL, Verilog, and schematic design files. Mixed-language designs are supported. For more information, see XST Synthesis Overview.
    •  Synplify and Synplify Pro
      Synplify and Synplify Pro are integrated third party synthesis tools that must be purchased separately from Synplicity, Inc. The Synplify software does not support projects that include mixed language source files. The Synplify Pro software supports projects that include mixed language source files, such as VHDL and Verilog sources files in the same project. The Synplify and Synplify Pro software do not support projects that include schematic design files. For more information, see Using Synplify or Synplify Pro Software for Synthesis.
    •  Precision
      Precision is an integrated third party synthesis tool that must be purchased separately from Mentor Graphics, Inc. The Precision software supports projects that include schematic design files and projects that include mixed language source files, such as VHDL and Verilog sources files in the same project. For more information, see Using Precision Software for Synthesis.
    Note Third party synthesis tools, such as Synplify and Precision, are only available as an option if the software is installed on your computer. If a synthesis tool is installed but does not appear as an option, make sure that the path to the tool is properly set in the Integrated Tools page of the Preferences dialog box. Image
  •  Simulator
    Specify the tool used for simulation and the language used for generating simulation netlists.
    •  ISim
      ISim is the simulator delivered with the ISE software. For more information about this tool, see the ISim Help. In the Help Viewer, click the Synchronize TOC button Image to view all related topics.
    •  ModelSim
      ModelSim is a third party tool that can be used in an integrated flow within the ISE software. For more information, see Using the ModelSim Simulator.
      Note After you purchase and install ModelSim, specify the correct executable path in the Integrated Tools page of the Preferences dialog box  prior to simulation. Image
    •  NC-Sim
      The NC-Sim simulator is a third party simulation tool that must be purchased separately from Cadence. It is not integrated with the ISE software and must be run standalone. For more information, see the documentation provided with the simulator.
    •  VCS
      The VCS simulator is a third party simulation tool that must be purchased separately from Synopsys. It is not integrated with the ISE software and must be run standalone. For more information, see the documentation provided with the simulator.
    •  Other
      Select Other if you are using a simulator that is not listed.
    Note If you are using a simulator that is not integrated with the ISE software, you must still specify your simulator. This ensures that all generated files are written in the correct format.
  •  Preferred Language
    Controls the default setting for process properties that generate HDL output, such as source files, intermediate files, or structural simulation netlists. If the Synthesis Tool and Simulator options are set to a single-language tool, the default language for generated HDL output files is automatically set. If both the Synthesis Tool and Simulator options are set to mixed-language (VHDL/Verilog) tools, you can use the Preferred Language property to select the language in which generated HDL output is created.
    •  Verilog
      Select this option if both the Synthesis Tool and Simulator are set to mixed-language and you want the default language to be Verilog.
    •  VHDL
      Select this option if both the Synthesis Tool and Simulator are set to mixed-language and you want the default language to be VHDL.
    •  N/A
      This option appears if both the Synthesis Tool and Simulator are set to a single language, because the generated language defaults are set based on the languages you selected for the Synthesis Tool and Simulator.
    Note Alternatively, you can change the target language on a per-process basis by selecting a process in the Processes pane of the Design panel, selecting Process > Process Properties, and setting the language in the property dialog box. For example, for the View HDL Functional Model process, you can specify the structural netlist target language in the Functional Model Properties dialog box.
  •  Property Specification in Project File
    Controls how properties are stored in the .xise file.
    •  Store non-default values only
      Select this option to store only non-default property settings in the .xise project file.
    •  Store all values
      Select this option to store all property settings, including those set to default values, in the .xise project file. This option is useful when working with source control systems and when moving projects between different ISE software versions, because the values for all properties are stored explicitly.
    Note For more information about the .xise project file, see Understanding the ISE Project File.
  •  Manual Compile Order
    By default, the RTL compilation order is automatically determined based on the ISE design hierarchy. This option allows you to override the default behavior and set the compilation order manually. Selecting this option disables all hierarchical parsing of HDL source files when they are added to the project, and the design source is displayed in a single flat list rather than hierarchically. For designs with a large number of HDL sources, this can make adding the source files faster. For more information, see Setting a Custom Compile Order.
  •  Enable Enhanced Design Summary
    Shows the number of errors and warnings for the entire project and for each of the Detailed Reports. For more information, see the Design Summary Overview.
  •  Enable Message Filtering
    Shows the number of messages you filtered. You must enable this option, filter messages, and then run the software to show the number of filtered messages. For more information, see Using Message Filters.
  •  Display Incremental Messages
    Shows the number of new messages for the most recent software run. You must enable this option, and then run the software to show the number of new messages. For more information, see the Design Summary Overview.
See Also
Creating a Project
Opening a Project

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