ISE
General Options
The following properties are available for the Generate Programming File process for FPGA devices.
  •  Run Design Rules Checker (DRC)
    Specifies whether or not the Design Rule Checker (DRC) is run. Before generating the final bitstream, it is important to use the DRC option in BitGen to evaluate the NCD file for problems that could prevent the design from functioning properly.
    By default, this property is set to True (checkbox is checked), and DRC is run.
  •  Create Bit File
    Specifies whether or not to create a design data or bitstream (BIT) file after you have verified the functionality and timing of your placed and routed design.
    By default, this property is set to True (checkbox is checked), and a file is created.
  •  Create Binary Configuration File
    Specifies whether or not to create a binary (BIN) file with programming data only. Use this option to extract and view programming data.  
    By default, this property is set to False (checkbox is blank), and a binary file is not created.
    Note  This configuration file is not intended for download to a PROM. For more information about generating a PROM file, see Generating a Target PROM or ACE File.
  •  Create ASCII Configuration File
    Specifies whether or not you want to create a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII ones and zeros. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA.
    By default, this property is set to False (checkbox is blank), and the file is not generated.
  •  Create IEEE 1532 Configuration File
    Specifies whether or not to create an ISC file. To use this property, you must set the FPGA Start-Up Clock to JTAG Clock in the Startup Options dialog box.
    By default, this property is set to False (checkbox is blank), and an ISC file is not created.
    Note  The ISC file is removed (deleted) when you select Project > Cleanup Project Files.
  •  Enable BitStream Compression
    Specifies whether or not to compress the bitstream file.
    By default, this property is set to False (checkbox is blank), and the file is not compressed.
  •  Enable Debugging of Serial Mode Bitstream
    Specifies whether or not to generate a debug bitstream file.
    By default, this property is set to False (checkbox is blank), and the file is not generated.
  •  Enable Cyclic Redundancy Checking (CRC)
    Specifies whether or not to run a check on the bitstream during the configuration process. When this property is set to True (checkbox is checked), Cyclic Redundancy Checking (CRC) is run on the bitstream during the configuration process. When this property is set to False (checkbox is blank), the device performs a simple pattern check in the configuration data.
    By default, this property is set to True (checkbox is checked).
  •  Retry Configuration if CRC Error Occurs (Spartan®-3A and Spartan-6 devices only)
    Note This property is only available if Enable Cyclic Redundancy Checking (CRC) is set to True (checkbox is checked).
    If selected, the FPGA will be reset when a CRC error is detected. This applies to master mode configuration only.
    By default, this property is set to False (checkbox is blank).
  •  Other BitGen Command Line Options (Advanced)
    Enter additional command line options. Separate multiple options with spaces. The options entered in this property appear first on the command line, before all other property options. Avoid setting duplicate property options.
    For more information about command line options, see the Command Line Tools User Guide.

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