Specifies the simulation language for the generated simulation model. The default Simulation Model Target is determined by language properties set for the project in the Design Properties dialog box. However, you can change the target language here.

Specifies a new speed grade for your design without re-running place and route. Changing the speed grade helps you determine if you need to target a faster device to meet your timing requirements, or if by using a slower speed grade you still meet timing constraints. You may also create a timing simulation netlist with absolute minimum timing values by selecting Absolute MIN if it is available for your target device.

This property shows the valid device speed grades for the device you are using, and defaults to the speed grade you have selected for your project.

Specifies whether to preserve the design hierarchy in the generated HDL file or to flatten the entire design. When this property is set to True (checkbox is checked), the hierarchy of the original design is retained on every level of hierarchy in which a KEEP_HIERARCHY attribute is attached in the output netlist.

By default, this option is set to True (checkbox is checked), and the design hierarchy is preserved.

Specifies whether or not to generate separate netlist and SDF files for each level of hierarchy retained in the design. This property is only available when the Retain Hierarchy property in this dialog box is set to True (checkbox is checked), and a KEEP_HIERARCHY attribute is used in the design.

When this property is set to True (checkbox is checked), you must create a custom DO file and associate the custom DO file in the Custom Do File property in the Simulation Properties dialog box if you plan to run a ModelSim simulation from within Project Navigator. If no DO file is associated, a custom DO file template called sample_custom.do is created in the project directory.

By default, this property is set to False (checkbox is blank).

Specifies whether or not to add the Global Tristate (GTS) signal, which forces all FPGA outputs to the high-impedance state, as an additional port on the top-level entity/module in the output file. This option should be used only if the global tristate net is not driven. For example, if you include a STARTUP_VIRTEX component in a design and have the GTS port of the component connected, do not set this property because the signal attached to the GTS port of the STARTUP_VIRTEX component drives the global tristate net.

By default, this property is set to False (checkbox is blank), and a global tristate net is not used as a port.

Specifies the port name for the additional port created to drive the Global Tristate (GTS) signal.

By default, this property is set to GTS_PORT. Do not use the name GTS, GSR, or the name of any existing wire or port as it may cause a conflict in the design.

Specifies whether or not to add the Global Set/Reset (GSR) net, which is connected to all flip-flops and latches in the physical design, as a port on the top-level entity in the output  file. This option should be used only if the global reset net is not driven. For example, if you include a component in a design and have the GSR part of the component connected, do not set this property because the signal attached to the GSR port of the component drives the global set/reset net.

By default, this property is set to False (checkbox is blank), and a global set/reset net is not used as a port.

Specifies a port name for the additional port created to drive the GSR signal. Do not use the name GTS, GSR, or the name of an existing wire or port as it may cause a conflict in the design.

By default, this property is set to GSR_PORT.

Specifies whether or not you want to create a template test bench file. The generated test bench template file is <entity_name>_<sim_model_name>.tvhd for a VHDL test bench or <module_name>_<sim_model_name>.tv for a Verilog test fixture, and the template file is placed in the project directory.

By default, this property is set to False (checkbox is blank), and a test bench template is not produced.

Specifies the instance name of the instantiated design used in the generated test bench template file. By default, the output files contain a top-level instance name of UUT. When simulating the design from within Project Navigator, UUT is the default design instance used for SDF annotation. If any other name is used for the design instance in your test bench, modify the UUT Instance Name property value in the ModelSim Simulation Properties dialog box.

If selected, path pulse buffers are inserted into the output netlist to prevent pulse swallowing. Pulse swallowing is seen on signals in back-annotated timing simulations when the pulse width is shorter than the delay on the input port of the component. For example, if a clock of period 5 ns (2.5 ns high/2.5 ns low) is propagated through a buffer, but in the SDF, the PORT or IOPATH delay for the input port of that buffer is greater than 2.5 ns, the output will be unchanged in the waveform window (e.g., if the output was "X" at the start of simulation, it will remain at "X").

Enter additional command line options. Multiple options are separated with a space. The options entered in this property appear first on the command line, before all other property options specified in the graphical user interface. Avoid setting duplicate options.

For more information about command line options, see the Command Line Tools User Guide. For more information on simulation techniques and methodologies, see the Synthesis and Simulation Design Guide.

Specifies the amount of time in which the Tristate on Configuration (TOC) signal is active, specified in nanoseconds. Enter a positive integer to specify how long all outputs to the design should remain in tristate at the start of simulation. The default value is 0 (inactive).

Specifies the amount of time in which the Reset On Configuration (ROC) signal is active, specified in nanoseconds. Enter a positive integer to specify how long the design should remain in a global set/reset state at the beginning of simulation.

By default, the global set/reset duration is 100 ns.

Specifies whether or not to generate the architecture portion only and omit writing the entity. This property is useful when generics are declared in the top-level entity declaration in the original RTL design as it allows the re-use of the original entity declaration for proper linking of the structural design to the test bench file.

By default, this property is set to False (checkbox is blank), and both entity and architectures are created in the resulting netlist.

Specifies whether or not to place a Verilog ’uselib directive in each resulting netlist file, with each directive pointing to the location of the SIMPRIM source files on the system. This option is not recommended for most simulators as the simulator should point to the path of the precompiled libraries.

By default, this property is set to False (checkbox is blank), and the SIMPRIM library path is not written to file.

Specifies whether or not to place a Verilog $sdf_annotate construct in each resulting netlist file.

When using ISim as your target simulator this property is set to False by default (checkbox is blank). For all other simulators, this property is set to True (checkbox is checked).

Specifies the path for the $sdf_annotate function written to the Verilog netlist file(s) which points to the corresponding SDF file to be annotated. In general, this option is needed only when the netlist or SDF file or both are moved and placed in different directories.

By default, this property is blank, and the SDF search path is set to the current working directory.

Specifies whether to use the Verilog escape naming method for signal names with invalid characters or to replace the invalid characters with underscores in order to create a valid netlist. When this property is set to True (checkbox is checked), name escaping does not occur, and, for example, the net name p140/empty becomes p140_empty because the forward slash is an invalid character. Most simulators can use the Verilog escape names; however, this property allows for netlist compatibility for those that do not.

By default, this property is set to False (checkbox is blank), and name escaping will occur.

Specifies whether or not to include UNISIM modules from the UNISIM library in each netlist file that results from a post-synthesis netlist simulation. This option enables you to bypass the need for specifying the library path during simulation. However, using this option increases the size of the netlist file and increases compile time.

By default, this property is set to False (checkbox is blank), and UNISIM models are not used.

Specifies whether or not to include SIMPRIM modules from the SIMPRIM library in each resulting netlist file. This option enables you to bypass the need for specifying the library path during simulation. However, using this option increases the size of the netlist file and increases compile time.

By default, this property is set to False (checkbox is blank), and SIMPRIM models are not used.

Specifies whether or not to include the glbl.v module in the output Verilog simulation netlist. If set to True (checkbox is checked), the glbl.v module will be written into the Verilog simulation netlist. If set to false, the output Verilog simulation netlist will not contain the glbl.v module. For more information on glbl.v, see the Synthesis and Simulation Design Guide. By default, this property is set to True (checkbox is checked).