The following properties are available for the simulation
processes and simulation model creation processes using the ModelSim simulator.
Note The available properties vary depending on the process you
have selected.
- Use Custom Do File
Specifies whether or not to use a custom DO file for simulation.
To run a simulation process, you must associate a DO file, which contains
a list of commands for the ModelSim simulator. Enable this property
to create a custom DO file. If you select this property, you must
specify a filename in the Custom Do File field.
By default,
this property is set to False (checkbox is blank), and a custom DO
file is not used in simulation.
Note Alternatively, you can enable
the Use Automatic Do File option to have Project Navigator generate a DO
file automatically.
- Custom Do File
Specifies the name of your custom DO file, which contains a
list of commands for the ModelSim simulator. The custom DO file is an
additional file to the DO files that are automatically generated when
the simulation process is started.
Enter the location and file
name of the custom DO file, or click the browse button and browse
to the Custom DO file in the Select File dialog box.
- Use Automatic Do File
Specifies whether or not to generate a macro file that compiles
all VHDL files in your project. This file also starts the simulation
process, and initializes the waveform display. This property is also
found in the
Simulation
Model Properties dialog box, and any setting made here is replicated
there.
If desired, you may add additional initialization commands
in the file called test_bench_file_name.udo. The file is automatically created the first time
the test bench is simulated.
By default, this property is set
to True (checkbox is checked) and a macro file is generated.
- Delay Values to be Read from SDF
Specifies which delay values will be read from the SDF file and
used for timing simulation.
- Setup Time
Specifies that setup time delays will be read from the SDF
file and used for the simulation. In the SDF file, these delays are
listed as Maximum (MAX) delays.
Setup time delays represent
the worst case operative conditions of the target device. Under these
conditions, the data paths of the device have the maximum delay possible,
while the clock path delays are the minimum possible relative to the
data path delays.
- Hold Time
Specifies that hold time delays will be read from the SDF file
and used for the simulation. In the SDF file, these delays are listed
as Minimum (MIN) delays.
Hold time delays represent the best
case operative conditions of the target device. Under these conditions,
the data paths of the device have the minimum delay possible, while
the clock path delays are the maximum possible relative to the data
path delays.
Note This property is available for the Simulate Post-Place
& Route Model process only.
- Custom Compile File List
Specifies a custom compile list file (a text file). The user-defined
compile list file that you define in this property is used to generate
the compile instructions for simulation. When the property is not
set, the ISE® software-generated compile file list is used.
The custom compile file lists the design files to be compiled
and the libraries associated with each file. Each file and library
pair is separated by a new line. The order of the design files determines
the compile order. The following is an example of the file format:
<library_name>;<file_name>
[<library_name>;<file_name>]
A library name is required. For Verilog files, you must
specify the work library. You cannot create your own Verilog libraries.
- Other VSIM/VLOG/VCOM Command Line Options (Advanced)
Enter additional command line options. Multiple options are
separated with a space. The options entered in this property appear
first on the command line, before all other property options specified
in the graphical user interface. Avoid setting duplicate property
options.
Note The command line options for vsim, vlog, and vcom
are described in the ModelSim documentation.
- Simulation Run Time
Specifies the amount of time to run the simulation. Following
are valid entries:
- [<timesteps> <time_units>] - Runs the simulation for <timesteps> <time_units> of time. <timesteps> is a positive
integer. <time_units> is ps, ns, us, ms,
or sec. For example, 2000 ns or 100 us.
- -all - Runs the
whole stimulus.
Note This property is available for the Simulation Model
processes only.
- Simulation Resolution (Advanced)
Specifies the simulation time resolution displayed in ModelSim.
You can specify a time unit between 1 fs and 100 sec. For Xilinx® simulation,
the default resolution of 1 ps is recommended, because some of the
models require this setting.
- VHDL Syntax (Advanced)
Specifies the VHDL language version to use during simulation.
By default, this property is set to 93.
- Use Explicit Declarations Only (Advanced)
When multiple definitions of a function exist, this option tells
the ModelSim compiler to use the explicit function definition instead
of the implicit function definition. By default, this property is
set to True (checkbox is checked).
- Use Configuration Name (Advanced)
Specifies whether or not you want to simulate a configuration
that is not the top module in the design. In your VHDL design file,
the Configuration construct enables you to specify an entity/architecture
pair. When this property is set to True (checkbox is checked), enter
the appropriate Configuration name you wish to use during simulation
in the next property.
By default, this property is set to False (checkbox is blank),
and the default top module is used for simulation.
- Configuration Name (Advanced)
Enter the Configuration Name associated with the entity/architecture
pair that you wish to use for simulation. If left as default, the
top module is used for simulation.
- Log All Signals in Simulation
Specifies whether or not to recursively log all the signals
in the design into the database file (.wlf extension). If set to True
(checkbox is checked), you can incrementally add more signals to the
waveform without having to restart the simulation.
By default,
this property is set to False (checkbox is blank), and signals are
not logged.
Note Setting this property to True significantly increases
the size of the database file and could result in slower simulation
runtimes.
- ModelSim Post-Map/Par/Fit UUT Instance Name
Specifies the instance name that was given to the instantiated
design in the test bench. This name is used by the ModelSim simulator
to annotate the SDF file. The default value is UUT.
You can
specify a different UUT instance name for each of the three processes:
Simulate Post-Map Model process, Post-Place & Route Model process,
and Simulate Post-Fit Model process.
Note This property is available
when using the Simulate Post-Map Model process, the Simulate Post-Place
& Route Model process, or the Simulate Post-Fit Model process.
- Generate SAIF File for Power Optimization/Estimation
Instructs ModelSim to create a value change dump (SAIF) file
for power estimation. By default, this property is set to False (checkbox
is blank).
Note This property is available for the Simulate Post-Place
& Route Model process only.
- SAIF File Name
Enter the SAIF file name that is generated. The default
file name is
xpower_time_sim.saif.
Note This
property is available for the Simulate Post-Place & Route Model
process only.