Specifies the signal that will be used to clock the startup sequence
at the end of the FPGA configuration process. Select a clock option
in the drop-down list.
CCLK
Synchronizes the startup sequence to the FPGA Configuration Clock
(CCLK). CCLK is internally generated if the FPGA is set for a Master
configuration mode; CCLK is an input if the FPGA is set for a Slave
configuration mode. This option should be set unless the device will
be configured through Boundary Scan (JTAG). Note that when generating
a configuration file that will be stored on a configuration PROM,
the Start-Up clock should be set for CCLK (even though the PROM itself
may be programmed through JTAG).
User Clock
Synchronizes the startup sequence to a user-defined signal connected
to the CLK pin of the STARTUP primitive, which must be instantiated
in the user design. Select this option when providing a startup clock
to the FPGA other than CCLK or the JTAG clock (this setup is rarely
used).
JTAG Clock
Synchronizes to the JTAG Test Clock (TCK). This clock sequences
the TAP controller which provides the control logic for JTAG. Select
this option when configuring the FPGA using JTAG. Note that an FPGA
that is configured from a PROM should not use this option, use CCLK
instead.
By default, this property is set to CCLK.
Enable Internal Done Pipe
Specifies whether or not the FPGA waits for the CFG_DONE signal
that is delayed by one clock cycle instead of waiting for the pin
itself. This option is available when the startup clock is running
at high speeds.
By default, this property is set to False (checkbox
is blank), and FPGA waits for the pin itself, and not the CFG_DONE
signal.
Done (Output Events)
Specifies the event that sets the DONE pin to high. Select
the applicable clock setting from the drop-down list.
By default,
this property is set to 4.
Enable Outputs (Output Events)
Specifies Startup phase that releases the I/O from tristate
condition and turns the configuration-related pins operational. Select
a number or one of the following settings from the drop-down list.
Done
Releases the I/O from tristate condition when the DoneIn signal
is High. DoneIn is either the value of the Done pin or a delayed version
if DonePipe=Yes.
Keep
Keeps the current value of the output enable.
By default, this property is set to 5.
Release Write Enable (Output Events)
Specifies the Startup phase that asserts the internal write
enable to flip-flops, LUT RAMs, and shift registers. It also enables
the BRAMs. Before the Startup phase both BRAM writing and reading
are disabled. Select a number or one of the following settings from
the drop-down list.
Done
Asserts global write enable (GWE) when the DoneIn signal is High.
DoneIn is either the value of the Done pin or a delayed version if
DonePipe=Yes.
Keep
Keep the current value of the GWE signal.
By default, this property is set to 6.
Wait for DLL Lock (Output Events)/Wait for PLL Lock (Output
Events)/Wait for DCM and PLL Lock (Output Events)
Selects the Startup phase to wait until DLLs/DCMs lock. When
working with Virtex®-6 devices, the name of this property is Wait for
PLL Lock (Output Events), and the Startup phase waits until PLLs/CMTs
lock. When working with Spartan®-6 devices, the name of this property
is Wait for DCM and PLL Lock (Output Events), and the Startup phase
waits until DCMs/PLLs lock.
By default, this property is set
to NoWait, and the Startup sequence does not wait for locking.
Note This property was formerly known as Release DLL (Output Events).
Wait for DCI Match (Output Events) (Spartan-3, Virtex-4, Virtex-5,
and Virtex-6 devices only)
Specifies a stall in this Startup cycle until Digitally Controlled
Impedance (DCI) match signals are asserted. When this
property is set to Auto, the DONE pin does not go high until the first
phase of the impedance adjustment process is complete.
By default,
this property is set to Auto.
Note This property was formerly
known as Match Cycle.
Drive Done Pin High
Specifies whether or not to drive the DONE pin high, as opposed
to using a Pull-up resistor, which is controlled by the Configuration
Pin Done property in the Configuration Options dialog box.
By default, this property
is set to False (checkbox is blank).