You can use the PlanAhead™ software
to floorplan your design after it has been synthesized. This allows
you to work with a design that has fully specified logic. In the PlanAhead software,
you can do the following:
- Create area constraints that apply to the placement of logic
on your device. Area (or placement) constraints are a way of restricting
where Place & Route (PAR) can place a particular piece of logic.
By reducing the search area for placing logic, the performance of
PAR may improve.
- View pin constraint information for the design, assign input
signals and output signals to package pins, specify I/O banks, specify
I/O standards, prohibit I/O locations, and create legal pin assignments
using design rule checks (DRCs).
- Create location constraints for global logic, including BUFG,
BRAM, MULT, PPC405, GT, DLL, and DCM.
Constraints are saved to a user
constraints file User Constraints File (UCF). You can create the UCF file prior to running
this process, as described in
Creating a Source
File, or you can allow the software to create an empty UCF
file.
Note This process is not supported for CPLDs.
To Floorplan a Design — Post-Synthesis
- In the Design panel, select Implementation from the Design View drop-down list.

- In the Hierarchy pane, select either the top module
or the associated UCF. - In the Processes pane, expand User Constraints.
- Double-click Floorplan Area/IO/Logic (PlanAhead).
The PlanAhead software opens. Project Navigator passes the synthesized
netlist source files to the PlanAhead software.
If a UCF file
is associated with your ISE® project, it is passed to the PlanAhead software
for modification. If a UCF file does not exist, an empty one is created
for you. If multiple UCF files exist, you are prompted to select the
file to which you want to add new constraints.
Existing constraints are modified in their respective files. For more information, see the “Analyzing the Design,” “Analyzing
Implementation Results,” and Floorplanning the
Design” chapters of the PlanAhead User Guide.Note After updating constraints in the PlanAhead software,
you must save the PlanAhead project and exit the PlanAhead software.
This updates the UCF files in the ISE project and updates the ISE project
status accordingly. If you do not save and exit from the PlanAhead software,
the ISE project and UCF files are not updated.
After running this process, you can do the following:
- Rerun the synthesize process.

- Implement your design.

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