Generating an IBIS Model

ISE

You can generate an Input Output Buffer Information Specification (IBIS) file that contains a pin list and models that are unique to your design. IBIS is a device modeling standard that allows for the development of behavioral models used to describe the signal behavior of device I/Os, while preserving proprietary circuit information.

The IBIS models can be used for the following:

To model best case and worst case models by using min, max current with the proper min, max ramp rates.
To simulate and predict electrical performance by providing I/V and V/T characteristics of the I/Os.

The IBISWriter tool, the tool that generates the model, requires a design source file as input:

For FPGA designs, the design source is a physical description of the design in a Native Circuit Description (NCD) file with an .ncd file extension.
For CPLD designs, the input is produced by the CPLD fitter tools and has a .pnx file extension.

To Generate an IBIS Model

In the Design panel, select Implementation from the Design View drop-down list.
In the Hierarchy pane, select the top module .
In the Processes pane, expand Implement Design.
Do one of the following:
- For an FPGA design, expand Place & Route.
- For a CPLD design, and expand Optional Implementation Tools.
Optional. Right-click the Generate IBIS Model process, and select Process Properties to set the IBIS Model Generation Properties.
Double-click Generate IBIS Model.

IBISWriter outputs a file_name.ibs ASCII file. This file consists of a list of pins used by your design, the signals internal to the device that connect to those pins, the I/O buffer models, and the package models for the IOBs connected to the pins.

Note For more information about IBISWriter, see the Command Line Tools User Guide.

After running this process, you can do either of the following:

View the generated IBIS model.
Read the IBIS model file into a signal integrity simulation tool for further simulation and analysis.