ISE
Generating a Post-Map Simulation Model
You can generate a simulation model after mapping your design. For this process, NetGen converts the output of the Map process (an NCD file) to a post-map simulation model (a structural SIMPRIM-based VHDL or Verilog file) and a Standard Delay Format (SDF) file. The SDF file contains estimates of the timing delays in your design. The simulation model and SDF files are then used in the Simulate Post-Map Model process to verify that functionality is correct at this stage of implementation.
To Generate a Post-Map Simulation Model
  1.  In the Design panel, select Implementation from the Design View drop-down list. Image
  2.  In the Hierarchy pane, select the top module Image.
  3.  In the Processes pane, expand Map.
  4.  Right-click Generate Post-Map Simulation Model, select Process Properties, and set the Simulation Model Properties.
    Note The HDL language selected in the Simulator Model Target property determines the language of the simulation model.
  5.  Double-click Generate Post-Map Simulation Model.
NetGen generates a simulation model (a VHDL or Verilog file) and an SDF file from the Map process results, which can be used as an input file for your simulator. The post-map simulation model is named <top_level_design_name>_map.v or .vhd.
Note For more information about NetGen, see the “NetGen” chapter of the Command Line Tools User Guide.
After running this process, you can run the Simulate Post-Map Model process. Image

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