Generating Post-Map Static Timing

ISE

You can optionally generate a post-map static timing report for your design. A post-map timing report lists the signal path delays in your design, derived from the design logic. This report can be useful in evaluating timing performance of the logic paths, particularly if your design does not meeting timing requirements.

Although route delays are not accounted for in this report, the logic delays can provide valuable information about the design, which can help identify problems with logic path timing. You can eliminate potential problems before investing time in examining routing delays. To eliminate problems, you may choose to redesign the logic paths to use fewer levels of logic, tag the paths for specialized routing resources, move to a faster device, or allocate more time for the path.

You must use a mapped FPGA design. You can also use a design that has been partially or completely placed, routed, or both. You can generate one of two report types:

Error report, which lists timing errors and associated net and path delay information.
Verbose report, which lists delay information for all nets and paths.

To Generate Post-Map Static Timing

In the Design panel, select Implementation from the Design View drop-down list.
In the Hierarchy pane, select the top module .
In the Processes pane, expand Implement Design, and expand Map.
Right-click Generate Post-Map Static Timing, and select Process Properties. Make the appropriate selections for the report details in the Post-Map Static Timing Report Properties.
Double-click Generate Post-Map Static Timing.

After running this process, you can run the Analyze Post-Map Static Timing process to open the static timing report and your design NCD file for further timing analysis in Timing Analyzer.

Note You can also view a text-based version of this report in the Design Summary. For more information, see Design Summary Overview and Viewing Messages and Reports.