ISE
Generating a Post-Place and Route Simulation Model
You can generate a simulation model after placing and routing your design. For this process, NetGen converts the Place & Route process results (an NCD file) to the simulation model (a structural SIMPRIM-based VHDL or Verilog file) and a Standard Delay Format (SDF) file. The SDF file contains true timing delay information for your design. The simulation model file and SDF file can be used to verify the functionality and timing of your design at this point in the design flow by using the Simulate Post-Place and Route Model process.
Note If you ran the Place and Route process with the Generate Post-Place & Route Simulation Model property set to Yes (default), you have already generated the simulation model.
To Generate a Post-Place & Route Simulation Model
  1.  In the Design panel, select Implementation from the Design View drop-down list. Image
  2.  In the Hierarchy pane, select the top module Image.
  3.  In the Processes pane, expand Place & Route.
  4.  Right-click Generate Post-Place & Route Simulation Model, select Process Properties, and set the Simulation Model Properties.
    Note The HDL language selected in the Simulator Model Target property determines the language of the simulation model.
  5.  Double-click Generate a Post-Place & Route Simulation Model .
NetGen generates a simulation model (a VHDL or Verilog file) and an SDF file from the Place & Route process results, which can be used as an input file for your simulator.  The post-place and route simulation model is named <top_level_design_name>_timesim.v or .vhd.
Note For more information about NetGen, see the “NetGen” chapter of the Command Line Tools User Guide.
After running this process, you can run the Simulate Post-Place & Route Model process. Image
Note For simulators not integrated with the ISE® software, see the documentation for your simulator for information on simulating your placed and routed design.

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