ISE
Generating a Post-Synthesis Simulation Model
You can generate a simulation model after synthesizing your design. For this process, NetGen converts the synthesis output (NGC) to a simulation model (a structural UNISIM-based VHDL or Verilog file). The simulation model can be used to verify that the functionality is correct after synthesis by running a post-synthesis simulation in your simulator.
To Generate a Post-Synthesis Simulation Model
  1.  In the Design panel, select Implementation from the Design View drop-down list. Image
  2.  In the Hierarchy pane, select the top module Image.
  3.  In the Processes pane, expand Synthesize - XST.
  4.  Right-click the Generate Post-Synthesis Simulation Model process, select Process Properties, and set the Simulation Model Properties.
    Note The HDL language selected in the Simulator Model Target property determines the language of the simulation model.
  5.  Double-click Generate Post-Synthesis Simulation Model.
NetGen generates a simulation model (a VHDL or Verilog file) from the Synthesize process results, which can be used as an input file for your simulator. The post-synthesis simulation model is named <top_level_design_name>_synthesis.v or .vhd.
Note For more information about NetGen, see the “NetGen” chapter of the Command Line Tools User Guide.
After running this process, you can run a post-synthesis simulation in your simulator.

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