ISE
Generating a Post-Translate Simulation Model
You can generate a simulation model after running the Translate process. For this process, NetGen converts the Translate process output (an NGD file) to a post-translate simulation model (a structural SIMPRIM-based VHDL and Verilog file). This simulation model is then used in the Simulate Post-Translate Model process to verify that design functionality is correct after the translation stage.  
To Generate a Post-Translate Simulation Model
  1.  In the Design panel, select Implementation from the Design View drop-down list. Image
  2.  In the Hierarchy pane, select the top module Image.
  3.  In the Processes pane, expand Translate.
  4.  Right-click Generate Post-Translate Simulation Model, select Properties, and set the Simulation Model Properties.
    Note The HDL language selected in the Simulator Model Target property determines the language of the simulation model.
  5.  Double-click Generate Post-Translate Simulation Model.
NetGen generates a simulation model (a VHDL or Verilog file) from the Translate process results, which can be used as an input file for your simulator. The post-translate simulation model is named <top_level_design_name>_translate.v or .vhd.
Note For more information about NetGen, see the “NetGen” chapter of the Command Line Tools User Guide.
After running this process, you can perform any of the following:
  •  Perform post-translate simulation. Image
  •  View the post-translate simulation model report. Image

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