Running the Map Process

ISE

After translation, you can run the Map process on your design. The Map process takes the Xilinx® Native Generic Database (NGD) file created during translation, runs a design rule check, and maps the logic design to a Xilinx FPGA. The results are output to a Native Circuit Description (NCD) file, which is used for placing and routing.

For an overview of the Map process, see the Implementation Overview for FPGAs. For detailed information about Map, see the “MAP” chapter of the Command Line Tools User Guide.

Note For Virtex®-5 devices, the design is automatically placed as part of the Map process. For all other devices, you can enable the Perform Timing-Driven Packing and Placement Map property if you want to place the design as part of the Map process.

To Run the Map Process

In the Design panel, select Implementation from the Design View drop-down list.
In the Hierarchy pane, select the top module .
Optional. In the Processes pane, expand the Implement Design process, right-click the Map process, and select Process Properties to set the Map Properties.
Double-click the Map process.

All processes necessary to successfully complete the Map process are run automatically. The Map process runs a design rule check on the design, and the logic design is mapped to a Xilinx FPGA. The resulting NCD file is output to the project directory.

After running Map, you can do any of the following:

View the Map report.
Generate post-Map static timing.
Analyze the Post-Map Static timing report.
Manually Place and Route your design.
Simulate the post-map simulation model to verify that the design was mapped correctly.
Run the Place and Route process.