ISE
Running the Place and Route (PAR) Process
You can run the
Place and Route (PAR) process after you have mapped your design. The
Place and Route process takes a mapped Native Circuit Description (NCD) file, places and routes
the design, and produces an NCD file to be used by the programming
file generator, BitGen.
For an overview of the Place and Route
process, see the Implementation Overview for FPGAs. For detailed information
about Place and Route, see the “PAR” chapter of the Command Line Tools User Guide.
Note For Spartan®-6, Virtex®-5, and Virtex-6 devices, the design is automatically
placed as part of the Map process, and the Place and Route process
only routes the design. For all other devices, you can enable the
Perform Timing-Driven Packing and Placement Map property if
you want to place the design as part of the Map process.
To Run the Place and Route Process
- In the Design panel, select Implementation from the Design View drop-down list.
- In the Hierarchy pane, select the top module
. - Optional. In the Processes pane, expand the Implement Design process, right-click the Place & Route process, and select Process Properties to set the Place and Route Properties.
- Double-click the Place & Route process.
All processes necessary to successfully complete the Place
and Route process are run automatically. The Place and Route process
outputs an NCD file that the programming file generator, BitGen, uses
to create a BIT file.
After running Place and Route, you can do any of the following:
- View the Place and Route report.
- Generate Post-Place & Route static timing.
- Analyze the Post-Place & Route Static timing report.
- Analyze timing and floorplan the design.
- View or edit the routed design.
- Run XPower Analyzer.
- Generate power data.
- Generate a post-Place and Route simulation model.
- Generate an IBIS model.
- Back-annotate pin locations.
- Run the Generate Programming File process.
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