ISE
Performing Post-Translate Simulation
You can perform post-translate simulation to verify that the functionality of the design is correct after the Translate process. This process uses the simulation model (a structured SIMPRIM-based VHDL or Verilog file) generated by NetGen. Post-Translate simulation can be performed on a simulation netlist or a source file available in the Post-Translate Simulation Design View, which may include any of the following:
  •  HDL test benches
  •  Simulation-only HDL source files, such as IP simulation models or external simulation models
  •  Structural HDL simulation netlists generated after the design is implemented
Note This process is optional and is typically used for debugging translation-related issues. It is available for FPGAs only.
To Perform Post-Translate Simulation
  1.  Run the Translate process. Image
  2.  In the Design panel, select Post-Translate Simulation from the Design View drop-down list. Image
  3.  In the Hierarchy pane, select a test bench file or select an HDL source file to simulate.
    To simulate a lower-level module of your design, you can set the Generate Multiple Hierarchical Netlist option in the Simulation Model Properties dialog box for the Generate Post-Translate Simulation Model process. After the simulation model netlist is generated, the netlist appears in the hierarchy under the test bench that instantiates it. Select this test bench to simulate.
    Note If you select a test bench to simulate, the necessary netlist will be generated for the top module of the design.
  4.  In the Processes pane, expand ModelSim Simulator.
  5.  Right-click Simulate Post-Translate Model, and select Process Properties.
  6.  In the Process Properties dialog box, set the following properties:
  7.  Double-click Simulate Post-Translate Model.
The following files are passed to your simulator:
  •  Test bench or test fixture file.
  •  Post-translation simulation model (VHDL or Verilog file).
Simulation is performed and the results are displayed in your simulator. If no stimulus is available, the design is simply compiled and loaded in the simulator. You must then create a stimulus file and perform a simulation on the design in the simulator.
Note For more information about using ModelSim, see the ModelSim Simulator documentation.
After running this process, you can perform any of the following:
  •  Analyze the results of the simulation process in your simulator.
  •  Rerun the Translate process. Image
  •  If the results are correct, run the Map process. Image

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