Use the Timing Analyzer view to perform the following functions
on your designs:
- Performs static timing analysis on FPGA designs.
- Timing analysis can be performed immediately after mapping,
placing, or routing an FPGA design.
- Timing Analyzer may be run interactively through Project Navigator’s
GUI or from the standalone application timingan.
- Timing Analyzer reports the delay along a given path or paths and
reports the slack based upon the specified timing requirements. It
organizes and displays data that allows you to analyze critical paths
in a circuit, the cycle time of the circuit, the delay along any specified
paths, and the path with the greatest delay. It also provides a quick
analysis of the effect speed grades, voltage, and temperature prorating
have on the same design.
- Timing Analyzer performs set up and hold checks. It works with
synchronous systems comprising synchronous elements and combinatorial
logic. In synchronous design, Timing Analyzer takes into account all path
delays, including clock-to-out and set up requirements, while calculating
the worst-case timing of the design.
- Timing Analyzer creates timing analysis reports based on design
timing constraints or user-specified paths within the
program.
- Timing reports have a hierarchical index to quickly jump to
different sections of the reports.
- Timing reports have a timing objects list to view and sort
all items associated with the current entry in the hierarchical index.
- Timing paths in the reports can be shown in the Technology
Viewer and FPGA Editor.
- Timing Analyzer is controlled through graphical user interface
features (menu commands).
- Timing Analyzer does not support CPLDs. You can run timingan_cpld for CPLD designs