ISE
Source File Types
To use and manage source files in Project Navigator, you must add the source files to the project. You can either create new source files in Project Navigator and automatically add them to the project, or you can add existing source files to the project. Following is a list of the supported source types. Some source types may not be available, depending on your design properties (top-level module type, target device, and synthesis tool).
Note For a list of all the file types generated by the ISE® software, see the "ISE Design Suite Files" appendix in the Command Line Tools User Guide.
File TypeExtensionIconDescriptionNew Source Wizard Behavior/Tool Launched
Block RAM Memory Map (BMM File).bmmImage
Used in PowerPC® and MicroBlaze™ processor designs to describe the organization of Block RAM memory.
Note Only one BMM Module is allowed per project.
Opens the file in the text editor you specify in the Editors page of the Preferences dialog box. The CPU executable code is automatically inserted in the configuration file during design implementation.
ChipScope Definition and Connection (CDC File).cdc  ImageContains generic information about the trigger and data ports of the ChipScope™ core.
Adds the file to the project. Double-click the CDC file in the Hierarchy pane of the Design panel to run the implementation process and launch the ChipScope Pro Core Inserter. For details, see the ChipScope Pro Tool Debugging Overview.
Note  The ChipScope Pro tool must be installed for this source type to be available.
Electronic Data Interchange Format (EDIF).edn, .edf, .edif, .sedifImageSpecifies the module in an industry standard file format.
N/A
Must be generated by a third-party design entry tool and added to the project.
Note  You can add an EDIF file as a top-level module or as a lower-level module. For information on adding lower-level EDIF modules to your design, see Working with Netlist-Based IP.
ELF.elfImage
Contains an executable CPU code image.
Note  Only one ELF file is allowed per project.
N/A
Must be generated by the Data2MEM command line tool and added to the project.
Embedded Processor.xmpImageEmbedded microprocessor project file created with Xilinx® Platform Studio (XPS).
Launches the Xilinx Platform Studio in which you can define the embedded processor system portion of your design. For details, see Working with Microprocessor and Peripheral IP and see the Embedded Development Kit Documentation.
Note You can add this source file to your project as a remote source, as described in Adding a Source File to a Project. You cannot add this source file as a copy.
Implementation Constraints File
also known as User Constraints File (UCF)
.ucfImageContains user-specified logical constraints.
Adds the file to the project. Double-click the UCF file in the Hierarchy pane of the Design panel, or double-click a Constraints Entry process in the Processes pane to open the file.
You can assign multiple UCFs to the top-level module. For details, see Constraints Entry Methods.
IP (Architecture Wizard).xawImageContains predefined logic functions that configure architecture features or modules.Launches one of the Xilinx Architecture Wizards in which you can define your IP. For details, see Working with Architecture Wizard IP.
IP (CORE Generator).xcoImageContains predefined logic functions.Launches one of the Xilinx IP core customization tools in which you can define your IP. For details, see Working with CORE Generator™ IP.
Memory Definition (MEM File).memImage
Used to define the contents of memory (RAMB4 and RAMB16).
Note Only one MEM file is allowed per project.
Opens the file in the text editor you specify in the Editors page of the Preferences dialog box. The CPU executable code is automatically inserted in the configuration file during design implementation.
Schematic.schImageContains a schematic design.Opens the schematic file in the Project Navigator Workspace. For details, see the Schematic Overview.
System Generator module.sgpImageContains Digital Signal Processing (DSP) system module created with System Generator for DSP.
N/A
Must be added to the project.
Note You can add this source file to your project as a remote source, as described in Adding a Source File to a Project. You cannot add this source file as a copy.
Targeted device, package, and speed gradeN/AImageShows the targeted device, package, and speed grade.N/A
UndefinedN/AImageContains an instantiated module that has not been added to the ISE project but is referenced by a source file in the ISE project.N/A
User DocumentMultiple file typesImageContains user information that is not implemented with the project, for example, supporting documentation.
N/A
Must be added to the project.
Verilog Module.vImageContains Verilog design code.Opens the file in the text editor you specify in the Editors page of the Preferences dialog box.
Verilog Test Fixture.vImageDefines the stimulus to the ports of an HDL file.Prompts you to associate the file with a Verilog source module and then opens a skeleton test bench file in the text editor you specify in the Editors page of the Preferences dialog box.
VHDL LibraryN/AImageContains a collection of VHDL packages.Adds a new directory to the vhdl library directory in the Libraries panel.
VHDL Module.vhdImageContains VHDL design code.Opens the file in the text editor you specify in the Editors page of the Preferences dialog box.
VHDL Package.vhdImageContains definitions, macros, sub-routines, supplemental types, subtypes, constants, functions, and other files.Opens the file in the text editor you specify in the Editors page of the Preferences dialog box.
VHDL Test Bench.vhd  ImageDefines the stimulus to the ports of an HDL file.Prompts you to associate the file with a VHDL source and then opens a skeleton test bench file in the text editor you specify in the Editors page of the Preferences dialog box.
Xilinx Native Generic Database.ngc, .ngoN/ASpecifies the module in a Xilinx proprietary file format.
N/A
Must be generated by a Xilinx IP generator tool (for example, CORE Generator software or System Generator for DSP) or generated directly by the XST software.
Note You can add an NGC/NGO netlist file as a top-level module or as a lower-level module. For information on adding lower-level NGC/NGO modules to your design, see Working with Netlist-Based IP.
See Also

© Copyright 1995–2010, Xilinx® Inc. All rights reserved.