Audio / Video / Image Processing

This book-length compendium of Virtex®-II Pro and Virtex-4 audio and video connectivity solutions for the broadcast industry contains the latest updated revisions of previously published serial video application notes as well as new designs not previously released. See the Preface for a list of the original application note numbers this volume replaces.

Design File(s):

• xapp514.zip

This application note shows how a Xilinx® CoolRunner™-II CPLD can be used as a simple logical switch that can quickly and reliably select between different MPEG video sources.

Design File(s):

• xapp944_source.zip.zip

MP3 portable players are the trend in music-listening technology. These players do not include any mechanical movements, thereby making them ideal for listening to music during any type of activity. MP3 is a digital compression technique based on MPEG Layer 3 which stores music in a lot less space than current CD technology. Software is readily available to create MP3 files from an existing CD, and the user can then download these files into a portable MP3 player to be enjoyed in almost any environment.

This TechXclusive article gives an overview of voice data convergence technologies, the benefits to the users and some of the significant challenges facing the designers of these systems.

This application note describes how to use Spartan®-3E FPGAs to implement various serial digital video interfaces commonly used in the professional video broadcast industry.

Design File(s):

• xapp1015.zip

This application note is a collection of audio and video connectivity solutions for the broadcast industry. It describes how to use Virtex®-5 FPGAs to implement serial digital video and audio interfaces commonly used in the professional video broadcast industry. The associated reference designs support many video rates and standards, and provide for embedded audio.

Design File(s):

• xapp1014.zip

This application note details bridging an XSVI interface to an AXI4-Stream interface, enabling video designs with Xilinx video IP cores and XSVI interfaces to use the AXI VDMA.

Design File(s):

• xapp521.zip

This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core.

Design File(s):

• xapp740_axi_video.zip

This guide introduces key concepts of the AXI protocol, gives an overview of what Xilinx tools you can use to create AXI-based IP, explains what features of AXI Xilinx has adopted and provide guidance on how to migrate your existing design to AXI. This document contains information about the AXI4 version of the core.

This application note demonstrates how to create a basic DDR3 MPMC design using the ISE® Design Suite Logic Edition tools, including Project Navigator (ProjNav) and the CORE Generator™ tool.

Design File(s):

• xapp739_axi_mpmc.zip

Step-by-step example using the PlanAhead™ tool to implement an AXI multi-port memory controller (MPMC) in a video test pattern generator on the KC705 board.

Design File(s):

• xapp788.zip

This application note covers the design considerations of a video system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core.

Design File(s):

• xapp741.zip

This application note demonstrates the creation of video systems by using Xilinx native video IP cores such as AXI Video Direct Memory Access (VDMA), Video Timing Controller (VTC), test pattern generator (TPG), and the DDR3 memory controller to process configurable frame rates and resolutions in Kintex™-7 FPGAs.

Design File(s):

• xapp742.zip

The purpose of this white paper is to describe how Spartan®-6 FPGAs address the needs of high-volume systems. The ability to connect efficiently and inexpensively to commodity memories, high-performance chip-to-chip interface capability, and innovative power down modes are just a few of the problems solved by high-performance, low-power, and low-cost Spartan-6 FPGAs.

This application note describes the implementation of a two-dimensional Rank Order filter. The reference design includes the RTL VHDL implementation of an efficient sorting algorithm.

Design File(s):

• xapp953.zip

This application note describes a digital camera reference design that uses a CoolRunner-II™ CPLD.

This application note describes the implementation of a YCrCb color space to an RGB Color space conversion circuit necessary in many video designs.

Design File(s):

• xapp931.zip

This application note describes the implementation of six circuits necessary to perform commonly used conversions between various chroma formats. It is accompanied by reference designs which include Generic RTL VHDL code.

Design File(s):

• xapp932.zip

This application note describes a set of reference designs able to transmit and receive DVI and HDMI data streams up to 1080 Mb/s using the native TMDS I/O interface featured by Spartan®-6 FPGAs.

This application note and reference design gives examples of a typical spread-spectrum clock for video applications using the Spartan®-6 FPGA DCM_CLKGEN primitive. DCM_CLKGEN can be used for fixed spread-spectrum generation without any logic or in a soft spread-spectrum solution using a state machine.

Design File(s):

• xapp1065.zip

New architectures developed by equipment vendors must be flexible, scalable, and show a roadmap towards lower power. This white paper discusses emerging standards and how FPGAs offer a flexible silicon platform for equipment vendors to meet the needs of a shifting marketplace.

This book-length compendium of Virtex®-II Pro and Virtex-4 audio and video connectivity solutions for the broadcast industry contains the latest updated revisions of previously published serial video application notes as well as new designs not previously released. See the Preface for a list of the original application note numbers this volume replaces.

Design File(s):

• xapp514.zip

This application note provides a functional description of VHDL source code for a N x N Digital Crosspoint Switch. The code is designed with eight inputs and eight outputs in order to target the 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higher density devices.

This document presents design techniques and reference circuits that power Virtex™-4 FX RocketIO™ multi-gigabit transceivers (MGTs) operating at data rates below 3.125 Gb/s.

This application note describes the implementation of a Virtex™-4 RocketIO bit-error rate tester (XBERT) reference design. The XBERT reference design generates and verifies non-encoded or 8B/10B-encoded high-speed serial data on one or multiple point-to-point links between Virtex-4 RocketIO Multi-Gigabit Transceiver (MGT) ports embedded within a single Virtex-4 FPGA.

Design File(s):

• xapp713.zip

This application note describes the implementation details of a bridge between a 133-MHz, 64-bit PCI-X interface and a 128 MB Double Data Rate (DDR), Small-Outline Dual Inline Memory Module (SODIMM) interface for Virtex™-4 devices. The reference design is capable of reading and writing up to four KB bursts of 64-bit data at 133 MHz.

Design File(s):

• xapp708.zip

This is a reference design for the Spartan™-3E Display Development Kit to assist in developing display panel products. The display solution FPGA design consists of a Video Input interface, Color Temperature Correction, Precise Gamma Correction, Image Dithering Engine, and an output interface.

Design File(s):

• xapp928.zip

Using CoolRunner™-II CPLDs with standard chipsets.

Uses CoolRunner™-II to control dot matrix LCD module. Includes design file.

Design File(s):

• xapp904_code.zip

This white paper gives an overall view of the various mainstream digital television standards and outlines related Forward Error Correction solutions available from Xilinx for cable, satellite, terrestrial, and mobile systems.

In today's world of modular networking and telecommunications design, it is becoming increasingly difficult to keep alignment with the many different and often changing interfaces, both inter-board and intra-board. Each manufacturer has their own spin on the way in which devices are connected. To satisfy the needs of our customers, we must be able to support all their interface requirements. For us to be able to make products for many customers, we must adopt a modular approach to the design. This modularity is the one issue that drives the major problem of shifting our bits from one modular interface to another.

This reference system tests the operation of the OPB CAN core in loopback mode.

Design File(s):

• xapp913.zip

The introduction of Spartan-3™ devices has created multiple changes in the evolution of embedded control designs and pushed processing capabilities to the “almost-free stage.” With these new FPGAs falling under $20, in volume, with over 1 million system gates, and under $5 for 100K gate-level units, any design with programmable logic has a readily available 8- or 16-bit processor costing less than 75 cents and 32-bit processor for less than $1.50. This white paper explores the benefits, system requirements, cost, design process, software and hardware architecture, and expansion strategy, along with many details of these systems.

This white paper discusses the FPD market and looks in closer detail at Plasma Display Panels and Liquid Crystal Displays in particular. An overview of where Xilinx devices fit in digital video systems is followed by a market overview of the flat panel display industry. The value proposition for Xilinx devices is presented, followed by a detailed discussion of the relationship of product features and resources to FPD system requirements.

An overview of CoolRunner™-II CPLD applications in the Digital Video Applications market.

The OPB USB 2.0 Device core performs the functionality of a USB high speed device and is compliant with the USB 2.0 Specification.

Design File(s):

• xapp997.zip

This application note targets Spartan™-3E devices in applications that require 4-bit or 5-bit transmit data bus widths and operate at rates up to 666 Mbps per line with a forwarded clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

Design File(s):

• xapp486.zip
• xapp486.zip

This application note targets Spartan®-3E/3A devices in applications that require 4-bit or 5-bit receive data bus widths and operate at rates up to 666 Mbps per line with a clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

Design File(s):

• xapp485.zip

This application note describes how to use Spartan®-3E FPGAs to implement various serial digital video interfaces commonly used in the professional video broadcast industry.

Design File(s):

• xapp1015.zip

This application note is a collection of audio and video connectivity solutions for the broadcast industry. It describes how to use Virtex®-5 FPGAs to implement serial digital video and audio interfaces commonly used in the professional video broadcast industry. The associated reference designs support many video rates and standards, and provide for embedded audio.

Design File(s):

• xapp1014.zip

This application note details bridging an XSVI interface to an AXI4-Stream interface, enabling video designs with Xilinx video IP cores and XSVI interfaces to use the AXI VDMA.

Design File(s):

• xapp521.zip

This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core.

Design File(s):

• xapp740_axi_video.zip

This application note demonstrates how to create a basic DDR3 MPMC design using the ISE® Design Suite Logic Edition tools, including Project Navigator (ProjNav) and the CORE Generator™ tool.

Design File(s):

• xapp739_axi_mpmc.zip

Step-by-step example using the PlanAhead™ tool to implement an AXI multi-port memory controller (MPMC) in a video test pattern generator on the KC705 board.

Design File(s):

• xapp788.zip

This application note covers the design considerations of a video system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core.

Design File(s):

• xapp741.zip

The triple-rate serial digital interface, which supports the SMPTE SD-SDI, HD-SDI, and 3G-SDI standards, is widely used in professional broadcast video equipment. This document describes how to implement triple-rate SDI interfaces with GTX transceivers in Virtex®-6 FPGAs.

Design File(s):

• xapp1075.zip

This application note and reference design provide a digital phase-locked loop (DPLL) solution using minimal external components and spare Virtex™-4 resources. The performance of the DPLL is superior to most integrated mixed-signal solutions. The DPLL design can be used in many different applications, including jitter reduction PLLs, clock multiplier PLLs, clock recovery PLLs, and clock generators.

Design File(s):

• xapp854.zip

This book-length compendium of Virtex®-II Pro and Virtex-4 audio and video connectivity solutions for the broadcast industry contains the latest updated revisions of previously published serial video application notes as well as new designs not previously released. See the Preface for a list of the original application note numbers this volume replaces.

Design File(s):

• xapp514.zip

Using Xilinx Spartan™-3E and Spartan-3A FPGAs, a National Semiconductor PHY, and a Xilinx video processing stack provides a very cost-effective and flexible approach to the challenges of multi-rate broadcast.

This application note describes how to use Spartan®-3E FPGAs to implement various serial digital video interfaces commonly used in the professional video broadcast industry.

Design File(s):

• xapp1015.zip

This application note is a collection of audio and video connectivity solutions for the broadcast industry. It describes how to use Virtex®-5 FPGAs to implement serial digital video and audio interfaces commonly used in the professional video broadcast industry. The associated reference designs support many video rates and standards, and provide for embedded audio.

Design File(s):

• xapp1014.zip

This application note describes a set of reference designs able to transmit and receive DVI and HDMI data streams up to 1080 Mb/s using the native TMDS I/O interface featured by Spartan®-6 FPGAs.

This document describes how to implement triple-rate SDI interfaces using Spartan®-6 FPGAs.

Design File(s):

• xapp1076_S6GTP_TripleRateSDI.zip

This application note delivers a system that is designed to replace external voltage controlled crystal oscillator (VCXO) circuits by utilizing functionality within each serial gigabit transceiver.