Wireless

This document describes the VHDL design for interfacing CoolRunner™-II CPLDs with low-power Mobile SDRAM memory devices. Mobile SDRAM is the ideal memory solution for wireless, handheld, and mobile computing applications, making this a perfect match with the Xilinx CoolRunner-II low-power CPLD family.

This document focuses on the design of a wireless transceiver using CoolRunner™ CPLDs. The wireless transceiver is implemented using the CoolRunner demo board. The wireless transceiver is the perfect application of the low-power capabilities of a CoolRunner CPLD.

This application note focuses on the baseband demodulation of Quadrature Amplitude Modulation (QAM) signals and, more specifically, on the use of a fractional rate decimator block. This application note also reviews polyphase decimating filter architectures and discusses the fractional rate decimator, its Xilinx System Generator 8.1i implementation, and its results.

Design File(s):

• xapp936.zip

Pseudo-random Noise (PN) generators are at the heart of every spread spectrum system. Many PN generators are required within Code Division Multiple Access (CDMA) base stations. PN generators are used to implement synchronization and uniquely code individual user signals across the transmission interface. PN generators are based upon Linear Feedback Shift Registers (LFSRs). Every Look-Up-Table (LUT) in a Virtex™ series or Virtex™-II series device can be configured as a 16-bit shift register (SRL16 macro). Hence, Virtex devices implement efficient LFSRs and deliver a significant reduction in resource utilization when compared with alternative flip-flop-only PLD structures.

Design File(s):

• xapp211.zip
• xapp211.zip

This application note describes the implementation of a processor lockstep system using embedded PowerPC™ 405 (PPC405) processors in Xilinx Virtex™-II Pro FPGAs, along with Xilinx software tools. To verify lockstep functionality, users learn how to build and run the Linux operating system with the MontaVista Linux Preview Kit and also how to probe signals in the lockstep system with Xilinx ChipScope™ Pro tools.

Design File(s):

• xapp564.zip
• xapp564.zip

FPGAs have been used in DSP applications for years; more recently FPGAs have been emerging as ideal co-processors for standard DSP devices. FPGAs provide tremendous computational throughput by using highly parallel architectures, and are hardware reconfigurable, allowing the designer to develop customized architectures for ideal implementation of their algorithms. The new generation of FPGAs developed using 90-nm process technology provide the designer with an even more cost-effective solution. This white paper takes a look at some common high-performance DSP functions and calculates their effective implementation costs.

This white paper discusses some of the advantages made available to the application design engineer by the Virtex™-5 family’s advanced approach to FPGA packaging.

Cell phone handsets (or “terminals,” as they’re called in Europe) are among the most dynamic products in the electronics market today. From their original analog roots, they have evolved into nearly pure digital devices with as much functionality as complex PDAs. Consumers who once evaluated handsets based on their ability to make high-quality local calls now take call clarity as a given. Their choices instead rest on characteristics ranging from a handset’s "skin" color to its ability to support streaming video. Buyers, even those shopping for low-cost handsets, increasingly demand these kinds of features: "extras" are well on their way to becoming standards. This shift puts manufacturers in a bind as they try to balance low cost with the ever-increasing consumer insistence on new features. Should customers pay for these features outright, or should their monthly payments subsidize the handset cost?

Today's data rates, exceeding 622 Mbps and reaching the 1 to 3.125 Gbps range across 20 inches or more of backplane trace, have made it challenging to pass data reliably over parallel buses. As a result, designers are now forced to shift from the use of parallel buses to utilizing more advanced serial interconnects; however, even serial technologies have limitations, especially at data rates beyond the 1 Gbps level, where new problems arise. This white paper presents methods of addressing these issues with programmable logic solutions for next generation serial backplanes.

Digital Up Converters (DUC) and Digital Down Converters (DDC) are key components of RF systems in communications, sensing, and imaging. This application note demonstrates how efficient DUC/DDC implementations can be created by leveraging Xilinx® DSP tools and IP portfolio for increased productivity and reduced development time.

Design File(s):

• xapp1113.zip

This application note describes how to utilize the dedicated deserializer(ISERDES) and serializer (OSERDES) functionalities in Virtex®-6 FPGAs to interface with analog-to-digital converters that have serial low-voltage differential signaling (LVDS) outputs and with digital-to-analog converters that have parallel LVDS inputs.

This application note provides designers using System Generator tools with options for source version control to determine the best tool flow and methodologies for team-based development.

Design File(s):

• xapp498.zip

This application note demonstrates how to efficiently implement Digitial Up and Down Converters(DUC/DDC) by leveraging the Xilinx® DSP IP portfolio. Two example DUC/DDC designs are provided for UMTS and CDMA2000 in both Spartan®-3A DSP and Virtex®-5 FPGAs.

Design File(s):

• xapp1018_cdma2000.zip
• xapp1018_wcdma.zip

The non-integer data recovery unit (NI-DRU) presented in this application note is specifically designed for RocketIO™ GTP and GTX transceivers in Virtex®-5 LXT, SXT, TXT, and FXT platforms and consists of look-up tables (LUTs) and flip-flops. The NI-DRU extends the lower data rate limit to 0 Mb/s and the upper limit to 1,250 Mb/s, making embedded high-speed transceivers the ideal solution for true multi-rate serial interfaces.

Design File(s):

• xapp875.zip

Topics include a description of the Zynq™-7000 architecture, how to use the Partial Reconfiguration and IDF capabilities of the PL to support various waveforms and reduce part count, and the power management features of the Zynq-7000 device.