Wireless

This application note describes a reference design of multi-channel digital up converters(DUCs) and digital down converters (DDCs) for CDMA2000 and UMTS base stations. The provided DSP algorithms meet base station specifications using digital-to-analog conversion rates of 61.44 MHz. Four-channel implementations are described that efficiently map the DSP algorithms into the resources of the Spartan™-3 family of FPGAs.

This application note describes the implementation of a processor lockstep system using embedded PowerPC™ 405 (PPC405) processors in Xilinx Virtex™-II Pro FPGAs, along with Xilinx software tools. To verify lockstep functionality, users learn how to build and run the Linux operating system with the MontaVista Linux Preview Kit and also how to probe signals in the lockstep system with Xilinx ChipScope™ Pro tools.

Today's serial backplane implementations support line rates ranging from 622 Mbps to 3.125 Gbps and are now approaching speeds in excess of 10 Gbps. A significant recent development is the emergence of standards to define serial backplanes. Whether proprietary or standards-based, serial backplanes present a very demanding signaling environment with high signal density, multiple connectors, and substantial trace lengths. Proving and characterizing the performance of any high-speed serial solution is critical, and MultiBERT provides a means of accomplishing this with Xilinx™ Multi-Gigabit Transceivers (MGTs).

Code Division Multiple Access (CDMA) is a rapidly expanding data transmission technique in the emerging Universal Mobile Telecommunications System (UMTS). This application note describes the implementation of a CDMA matched filter using the architectural features of the Virtex™ series, Virtex™-II series, and Spartan™-II family of devices.

Pseudo-random Noise (PN) generators are at the heart of every spread spectrum system. Many PN generators are required within Code Division Multiple Access (CDMA) base stations. PN generators are used to implement synchronization and uniquely code individual user signals across the transmission interface. PN generators are based upon Linear Feedback Shift Registers (LFSRs). Every Look-Up-Table (LUT) in a Virtex™ series or Virtex™-II series device can be configured as a 16-bit shift register (SRL16 macro). Hence, Virtex devices implement efficient LFSRs and deliver a significant reduction in resource utilization when compared with alternative flip-flop-only PLD structures.

This document describes the VHDL design for interfacing CoolRunner™-II CPLDs with low-power Mobile SDRAM memory devices. Mobile SDRAM is the ideal memory solution for wireless, handheld, and mobile computing applications, making this a perfect match with the Xilinx CoolRunner-II low-power CPLD family.

This document focuses on the design of a wireless transceiver using CoolRunner™ CPLDs. The wireless transceiver is implemented using the CoolRunner demo board. The wireless transceiver is the perfect application of the low-power capabilities of a CoolRunner CPLD.

Linear Feedback Shift Registers (LFSRs) are commonly used in applications where pseudo-random bit streams are required. LFSRs are the functional building blocks of circuits like the pseudo-random noise (PN) code generator (XAPP211) and Gold code generators (XAPP217) commonly used in Code Division Multiple Access (CDMA) systems. This application note describes two implementations of an LFSR using the SRL16 (Shift Register Look-Up Table) primitive for area-efficient designs. The first LFSR implementation describes the parallel output access and parity calculation; the second describes the multi-cycle output access and sequential parity calculation. This application note covers the Virtex™ series, the Virtex™-II series, and the Spartan™-II family of devices.

Gold code generators are used extensively in Code Division Multiple Access (CDMA) systems to generate code sequences with good correlation properties. This application note describes the implementation of Gold code generators in Virtex™>, Virtex™-E, Virtex™-EM, Virtex™-II and Spartan™-II devices. The Gold code generators use efficiently-implemented Linear Feedback Shift Registers (LFSRs) in both the Virtex/Virtex-II series and Spartan-II family using the SRL16 macro.

This application note focuses on the baseband demodulation of Quadrature Amplitude Modulation (QAM) signals and, more specifically, on the use of a fractional rate decimator block. This application note also reviews polyphase decimating filter architectures and discusses the fractional rate decimator, its Xilinx System Generator 8.1i implementation, and its results.

This application note demonstrates how to efficiently implement Digitial Up and Down Converters(DUC/DDC) by leveraging the Xilinx DSP IP portfolio. Two example DUC/DDC designs are provided for UMTS and CDMA2000 in both Spartan™-DSP and Virtex™-5 FPGAs.

The enterprise, SOHOs, and homes are demanding mobility and portability with high-bandwidth data, voice, and video access. This has led to the introduction of wireless LAN technologies, which attempt to provide exactly that. In the 2.4 GHz frequency band, IEEE 802.11b is “the“ wireless LAN solution in the market. However the 5 GHz frequency has two possible contending technologies — IEEE 802.11a and HiperLAN2. This white paper explains the state of affairs in the wireless LAN market, the underlying technology behind the different types of wireless LANs, the over-utilized 2.4 GHz spectrum, the migration to 5 GHz band, which technology will succeed, and how Xilinx Spartan-II are ideal for this market place.

This paper provides an overview of satellite modem technologies and standards, and discusses how the Internet is driving the deployment of this technology. The Xilinx device families targeted at these high volume applications include XC9500 CPLDs and Spartan-II FPGAs.

FPGAs have been used in DSP applications for years; more recently FPGAs have been emerging as ideal co-processors for standard DSP devices. FPGAs provide tremendous computational throughput by using highly parallel architectures, and are hardware reconfigurable, allowing the designer to develop customized architectures for ideal implementation of their algorithms. The new generation of FPGAs developed using 90-nm process technology provide the designer with an even more cost-effective solution. This white paper takes a look at some common high-performance DSP functions and calculates their effective implementation costs.

This white paper discusses some of the advantages made available to the application design engineer by the Virtex™-5 family’s advanced approach to FPGA packaging.

Cell phone handsets (or “terminals,” as they’re called in Europe) are among the most dynamic products in the electronics market today. From their original analog roots, they have evolved into nearly pure digital devices with as much functionality as complex PDAs. Consumers who once evaluated handsets based on their ability to make high-quality local calls now take call clarity as a given. Their choices instead rest on characteristics ranging from a handset’s "skin" color to its ability to support streaming video. Buyers, even those shopping for low-cost handsets, increasingly demand these kinds of features: "extras" are well on their way to becoming standards. This shift puts manufacturers in a bind as they try to balance low cost with the ever-increasing consumer insistence on new features. Should customers pay for these features outright, or should their monthly payments subsidize the handset cost?

Today's data rates, exceeding 622 Mbps and reaching the 1 to 3.125 Gbps range across 20 inches or more of backplane trace, have made it challenging to pass data reliably over parallel buses. As a result, designers are now forced to shift from the use of parallel buses to utilizing more advanced serial interconnects; however, even serial technologies have limitations, especially at data rates beyond the 1 Gbps level, where new problems arise. This white paper presents methods of addressing these issues with programmable logic solutions for next generation serial backplanes.