Memory Interface and Controller

This document provides an overview of all Xilinx memory interface application notes that support Virtex™ Series FPGAs. In addition, some key features of the prevalent memory technologies are also provided. For each application note, the data capture technique, clocking scheme, FPGA resources used, and supported memory technology are described briefly.

This application note describes a method to configure Xilinx FPGAs, such as Spartan®-IIE and Spartan-3 FPGAs, using inexpensive small Serial Peripheral Interface (SPI) flash memories.

This application note describes how to use a Virtex™-II Pro device to interface to Common I/O (CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices. The reference design targets two CIO DDR RLDRAM II devices at a clock rate of 270 MHz with data transfers at 540 Mb/s per pin.

This application note describes a DDR2 SDRAM memory interface for Virtex™-II Pro FPGAs.

This application note describes a 200 MHz four-word burst QDR II SRAM interface implemented in a Virtex-II Pro™ XC2VP20 FF1152 –6 device.

This application note describes a Redundant Array of Independent Disks (RAID) which is a hard-disk drive (HDD) array where part of the physical storage capacity stores redundant information. Data is regenerated from the physical storage if one or more of the disks in the array (including a single failed disk sector)or the access path to it fails.

This application note describes how memories wider than 36 bits can be efficiently implemented in the Virtex™-II and Spartan™-3 architectures. The clock-doubling method used is similar to the method described for quad-port memories in XAPP228. The resulting memories are used in either dual-port or single-port mode.

Quad Data Rate (QDR™Synchronous Static RAM (SRAM) is one of the highest bandwidth solutions available for networking and telecommunications applications. This low-cost, high-performance solution is ideal for applications requiring memory buffering, traffic management, look-up tables, or link lists. This application note describes an implementation of a QDR SRAM controller for Virtex™-II devices using a source synchronous solution.

Designed to be implemented in a Virtex™-II FPGA, the Virtex-II SiberBridge is a register transfer logic (RTL) design example demonstrating a reference interface between a 32-bit host (typically a network processor) and the SiberCAM™ device, or a cascade of SiberCAM devices. The SiberCAM device is a large capacity content addressable memory (CAM) product of SiberCore Technologies. The SiberBridge provides a way to initiate searches, obtain search results, and perform table maintenance operations for the SiberCAM, all using a single 32-bit synchronous SRAM or a ZBT SRAM interface. The SiberBridge is intended as a reference design having a low-gate count.

This document describes a reference design for interfacing CoolRunner™-II CPLDs with double data rate (DDR) SDRAM memory devices. The built reference design is capable of 100 MHz operation.

This application note describes the use of a Xilinx CoolRunner™ XPLA3 CPLD to implement a NAND Flash memory interface. CoolRunner CPLDs are the lowest power CPLD available and the ideal target device for memory interface applications.

Describes the hardware accelerator for RAID6 parity generation / data recovery controller with ECC and MIG DDR2 controller.

On-die termination (ODT) promises higher signaling rates for printed circuit board (PCB) inter-chip interfaces through improved signal integrity. However, when using ODT, there is sometimes an associated power penalty. This application note explains the reason for the power penalty and suggests a simulation technique for comparing the signal integrity and power dissipation of internally and externally terminated versions of an interface.

This application note provides information on using the PLB DDR2 with OPB Central DMA.

This application note describes how to use a Virtex™-5 device to interface to Common I/O(CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices.

This application note describes a 200-MHz DDR SDRAM memory controller implemented in a Virtex™-5 device. This reference design uses the Virtex-5 ChipSync features to calibrate and adjust read data timing. A straightforward backend user interface is provided to allow integration into a complete FPGA design.

This application note shows how the 32-bit MicroBlaze™ processor can easily access wide data width memories. The design is also suitable for use with the IBM PowerPC™ (PPC405) processor because it connects to the On-chip Peripheral Bus (OPB). The reference design provides a modification to an existing Xilinx EDK SDRAM interface, enabling a 32-bit processor to access a 64-bit data bus.

This application note describes a 267 MHz (and above) DDR2 controller implementation in a Virtex™-4 device interfacing to a Micron DDR2 SDRAM device.

This Application Note describes a data capture technique for a high-performance DDR2 SDRAM interface. This technique uses the Input Serializer/Deserializer (ISERDES) and Output Serializer/Deserializer (OSERDES) features available in every Virtex™-4 I/O. This technique can be used for memory interfaces with frequencies of 267MHz (533Mb/s) and above.

This application note describes a CIO DDR RLDRAM II controller design implemented in a Virtex®-4 device.

This application note describes a DDR SDRAM controller implemented in a Virtex™-4 XC4VLX25 FF668 -10 device. This implementation uses direct clocking for data capture and an automatic calibration circuit to adjust delay on the data lines.

This application note describes the implementation details of a bridge between a 133-MHz, 64-bit PCI-X interface and a 128 MB Double Data Rate (DDR), Small-Outline Dual Inline Memory Module (SODIMM) interface for Virtex™-4 devices. The reference design is capable of reading and writing up to four KB bursts of 64-bit data at 133 MHz.

This application note describes the implementation and timing details of a four-word burst QDR II SRAM interface for Virtex®-4 devices. The synthesizable reference design leverages the unique I/O and clocking capabilities of the Virtex-4 family to achieve performance levels up to 300 MHz (600 Mb/s), resulting in an aggregate throughput for each 36-bit memory interface of 43.2 Gb/s.

This application note demonstrates the use of the Multi CHannel (MCH) On Chip Peripheral Bus (OPB) External Memory Controller (EMC) in a MicroBlaze processor system.

This application note describes the controller and data capture technique for high-performance DDR2 SDRAM interfaces. This data capture technique uses the Input Serializer/Deserializer(ISERDES) and Output Double Data Rate (ODDR) features available in every Virtex®-5 I/O.

This application note describes a 267-MHz DDR2 controller implementation in a Virtex™-4 device interfacing to a Micron DDR2 SDRAM device.

This application note describes the DDR2 SDRAM physical layer design using the direct-clocking technique in a Virtex™-4 device. The direct-clocking technique utilizes some of the architectural features unique to the Virtex-4 family, for example, the 64-tap absolute delay line provided in each I/O block (IOB).

Designing high-speed memory interfaces is a challenging task. Xilinx makes it simple to design such interfaces using the Virtex-II™ and Virtex-II Pro™ FPGAs. This application note discusses the challenges presented by this task, together with various techniques that can be used to overcome them, while illustrating the key concepts in implementing any memory interface. All examples used in this application note assume a DDR-1 interface on an XC2VP20FF1152-6 Virtex-II Pro FPGA. The interface speed is 200 MH.

This application note provides implementation guidelines for DDR interfaces using the Digital Clock Manager (DCM) and local inversion clocking techniques for Virtex-II™ Pro devices.

Data regeneration is an important function in RAID controllers and is best performed by dedicated hardware under the control of a microprocessor. The Virtex-II Pro™ FPGA can perform both the hardware and software functions required for a RAID parity generator and data regeneration controller. This reference design uses burst mode SYNCBURST™SRAM memory accesses and an internal block SelectRAM+™ memory to provide an extremely efficient hardware design in a Virtex-II Pro FPGA.

This application note utilizes the Virtex-II Pro™ transceivers and the Xilinx Aurora Protocol Engine to provide a multi-ported interface to a shared memory system in a backplane environment. Multiprocessor systems are often encountered in backplane systems, and distributed processing applications require access to a shared memory across a backplane bus. Utilization of a hardware test-and-set lock mechanism, along with a software protocol to test for a semaphore grant prior to accessing the shared memory, guarantees atomic access to the shared memory.

This application note describes the implementation of an Error Correction Control (ECC) module in a Virtex™-II, Virtex-II Pro, Virtex-4, and Virtex-5 device. The design can detect and correct all single bit errors (in a code word consisting of either 64-bit data and 8 parity bits, or 32-bit data and 7 parity bits), and it can detect double bit errors in the data. This design utilizes Hamming code, a simple yet powerful method for ECC operations. As a result, this design offers exceptional performance and resource utilization.

The DDR2-400 (200 MHz clock) memory interface discussed in this application note is derived from the default output of MIG. Xilinx has validated this interface in Spartan™-3A FPGAs with the higher speed grade (-5) assembled on Spartan-3A Starter Kits. The validation results also apply to Spartan-3AN and Spartan-3A DSP FPGAs.

This application note describes how to build a Spartan™-3E embedded system that is used to determine the optimal phase shift of a DDR memory feedback clock.

This document can help designers obtain more accurate I/O timing data without the need for board-level IBIS or SPICE simulations. Until recently, Xilinx specified outputs into a lumped capacitive load. However, since rise and fall times force board interconnect to be considered transmission lines, a lumped capacitive load is no longer relevant (see the TechXclusives document on this for more detail).

This white paper discusses the various memory interface controller design challenges and Xilinx solutions, including how to use the Xilinx software tools and hardware-verified reference designs to build a complete memory interface solution for your own application, from low-cost DDR SDRAM applications to higher-performance interfaces like the 667Mb/s DDR2 SDRAMs.

This white paper discusses some of the advantages made available to the application design engineer by the Virtex™-5 family’s advanced approach to FPGA packaging.

This application note describes how to retrieve user-defined data from Xilinx configuration PROMs (XC18V00 and Platform Flash devices) after the same PROM has configured the FPGA. The method to add user-defined data to the configuration PROM file is also discussed.