User Guides

This guide describes the RocketIO™ GTX transceivers available in the Virtex®-5 FXT platform devices.

This guide provides complete packing information for Virtex®-4 QPro™-V (QV) Radiation-Hardened FPGAs in 1.00-mm pitch ceramic flip-chip column grid array (CF) packages. Virtex-4 QV Radiation Hardened FPGAs are offered exclusively in ceramic flip-chip column grid array (CF) packages that are optimally designed for improved thermal cycle reliability.

This user guide describes the basic function and operation of the MPEG-4 Simple Profile Decoder core and contains information about designing, customizing, and implementing the core

The H.264 Motion Estimation Engine Version 1.0 is a fully functional netlist implemented on Xilinx® FPGAs.

This guide describes the Platform Flash XL feature set and demonstrates the common configuration mode setups supported.

This guide describes the Virtex®-5 FPGA RocketIO™ Transceiver Signal Integrity Simulation (SIS) Kit.

This document describes the behavior of the I/Os under various operating conditions. It describes how to use the different termination modes, how to understand thresholds, and how loading affects the I/Os.

This user guide is a detailed functional description of XtremeDSP™ Solution Spartan™-3A DSP technology.

This guide explains how to install the Xilinx® family of USB programming cables, including information related to installing Xilinx USB cables with the Xilinx Integrated Software Environment (ISE) software and Xilinx ISE® WebPACK™ software.

For Spartan®-3AN FPGA applications that read or write data to or from the In-System Flash memory after configuration.

Describes the configuration features of the Spartan®-3 Generation FPGAs. Includes the Spartan-3A, Spartan-3AN, Spartan-3A DSP, Spartan-3E, and Spartan-3 FPGA families.

Functional description of the Spartan®-3 generation FPGA architecture and how to use it. Includes the Spartan-3A, Spartan-3AN, Spartan-3A DSP, Spartan-3E, and Spartan-3 platforms.

The Virtex™-4 RocketIO Bit Error Rate Tester (XBERT) Reference Design for the ML42x development platforms demonstrates a serial link between two or more Virtex-4 RocketIO Multi-Gigabit Transceiver (MGT) ports embedded within a single Virtex-4 FPGA. This user guide provides instructions to set up and operate the XBERT reference design on the ML421, ML423, ML424 and ML425 platforms.

This guide provides information on PCB design for Virtex®-5 devices, with a focus on strategies for making design decisions at the PCB and interface level.

This guide describes the RocketIO™ GTP transceivers available in the Virtex™-5 LXT and SXT platform devices.

This user guides describes Virtex®-5 device pinouts and package specifications, and pinout diagrams and thermal data.

This document describes the Virtex®-5 DSP48E slice.

This guide describes the System Monitor functionality available in all Virtex®-5 devices.

This all-encompassing configuration guide includes detailed information on the Virtex®-5 FPGA configuration interfaces (JTAG, Serial, SelectMAP, SPI and BPI), and it discusses flows and techniques for bitstream encryption, readback and reconfiguration.

The Virtex®-5 FPGA User Guide includes chapters on clocking resources, clock management technology, phase-locked loops, block RAM, Configurable Logic Blocks (CLBs), SelectIO™ resources, and SelectIO logic resources.

The Platform Flash PROM User Guide describes advanced features of the Platform Flash PROM family of devices. This guide also includes information on configuration setups, generation of the files used to program this PROM family, and other design considerations.

This user guide provides instructions for setting up and operating the RocketIO™ X BERT reference design on MK322 and MK325 platforms.

This report is published by Xilinx to provide insight to our customers regarding the reliability of Xilinx products.

This document discusses thermal, electrical, moisture, and soldering characteristics of Xilinx device packages.

The reference design described in this document serves as an introduction to Xilinx embedded solutions, specifically the PowerPC™ processor. It also covers the Xilinx Platform Studio™ tool and the included Base System Builder™ wizard. Finally, this reference design illustrates how to add custom or third-party IP to the PowerPC APU interface.

The Virtex™-4 RocketIO™ Multi-Gigabit Transceiver User Guide provides the product designer with the detailed technical information needed to successfully implement the RocketIO MGT in Virtex-4 designs.

This guide describes Virtex®-4 device pinouts and package specifications; it also includes pinout diagrams and thermal data.

The guide describes the XtremeDSP™ slice and includes reference designs for using the DSP48 math functions and various FIR filters.

This guide describes the PCB guidelines for the Virtex®-4 family. It covers SelectIO™ interface signaling, RocketIO™ transceiver signaling, power distribution systems, PCB breakout, and parts placement.

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bit-stream encryption, Boundary-Scan and JTAG configuration, and reconfiguration techniques.

The Virtex®-4 FPGA User Guide includes chapters on Clocking Resources, Digital Clock Manager (DCM), Phase-Matched Clock Dividers (PMCD), Block RAM and FIFO memory, Configurable Logic Blocks (CLBs), SelectIO™ resources, and SelectIO logic resources.

The RocketIO BERT reference design for ML32x platforms demonstrates a 2.5 Gbps to 3.125 Gbps serial link between two RocketIO multi-gigabit transceiver (MGT) ports, embedded within a single Virtex-II Pro FPGA.

RocketIO™ X transceivers with flexible, programmable features allow a multi-gigabit serial transceiver (MGT) to be easily integrated into any Virtex-II Pro™ X design.

This user guide discusses managing hardware and software data with Virtex™-II Pro devices as well as Virtex-II Pro wake-up solutions

This User Guide provides a general overview as well as digital design considerations, analog design considerations, simulation and implementation options, timing model, valid data/control characters, and RocketIO-related online publications.

This document contains information about Timing Models, Design Considerations, Configuration, PCB Design Considerations, BitGen and PROMGen Switches, and XC18V00 Series PROMs.

This document discusses timing models, design considerations, configuration, PCB design considerations, BitGen and PROMGen Switches and Options, and PROM information.