VERILOG Project Status | |||
Project File: | Verilog.ise | Current State: | Synthesized |
Module Name: | v5_sysmon |
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No Errors |
Target Device: | xc5vlx30-3ff324 |
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2 Warnings |
Product Version: | ISE 9.2i |
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Wed 11. Jul 16:53:51 2007 |
VERILOG Partition Summary | |||
No partition information was found. |
Device Utilization Summary (estimated values) | |||
Logic Utilization | Used | Available | Utilization |
Number of bonded IOBs | 13 | 220 | 5% |
Number of BUFG/BUFGCTRLs | 1 | 32 | 3% |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | Wed 11. Jul 16:52:31 2007 | 0 | 2 Warnings | 0 |
Translation Report | |||||
Map Report | |||||
Place and Route Report | |||||
Static Timing Report | |||||
Bitgen Report |