Virtex-4

This document is a brief introduction to the features of the Virtex®-4 family. It contains the device summary, packaging options, and ordering information.

This data sheet specifies the electrical characteristics of the Virtex®-4 Family, including absolute maximum ratings, recommended operating conditions, supply requirements, and switching characteristics.

This guide describes Virtex®-4 device pinouts and package specifications; it also includes pinout diagrams and thermal data.

All package files are ASCII files in zip format.

This guide serves as a technical reference describing the hardware interface to the PowerPC® 405 processor block. It contains information on input/output signals, timing relationships between signals, and the mechanisms software can use to control the interface operation.

This document provides an introduction as well as operational concepts, user programming model, PPC405 privileged-mode programming model, memory-system management, and virtual-memory management.

Summary of the reliability test data and results for Xilinx devices updated four times per year.

The Virtex®-4 FPGA User Guide includes chapters on Clocking Resources, Digital Clock Manager (DCM), Phase-Matched Clock Dividers (PMCD), Block RAM and FIFO memory, Configurable Logic Blocks (CLBs), SelectIO™ resources, and SelectIO logic resources.

Design File(s):

• ug070.zip

This guide describes Virtex®-4 device pinouts and package specifications; it also includes pinout diagrams and thermal data.

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bit-stream encryption, Boundary-Scan and JTAG configuration, and reconfiguration techniques.

The guide describes the XtremeDSP™ slice and includes reference designs for using the DSP48 math functions and various FIR filters.

Design File(s):

• ug073_c02.zip
• ug073_c03.zip
• ug073_c04.zip
• ug073_c05.zip
• ug073_c06.zip
• ug073_c07.zip

The Virtex®-4 RocketIO™ Multi-Gigabit Transceiver User Guide provides the product designer with the detailed technical information needed to successfully implement the RocketIO Multi-Gigabit Transceiver in Virtex-4 designs.

This guide describes the Embedded Tri-Mode Ethernet Media Access Controller (MAC) available in the Virtex®-4 FX family.

This guide describes the PCB guidelines for the Virtex®-4 family. It covers SelectIO™ interface signaling, RocketIO™ transceiver signaling, power distribution systems, PCB breakout, and parts placement.

The Virtex™-4 RocketIO Bit Error Rate Tester (XBERT) Reference Design for the ML42x development platforms demonstrates a serial link between two or more Virtex-4 RocketIO Multi-Gigabit Transceiver (MGT) ports embedded within a single Virtex-4 FPGA. This user guide provides instructions to set up and operate the XBERT reference design on the ML421, ML423, ML424 and ML425 platforms.

The reference design described in this document serves as an introduction to Xilinx embedded solutions, specifically the PowerPC™ processor. It also covers the Xilinx Platform Studio™ tool and the included Base System Builder™ wizard. Finally, this reference design illustrates how to add custom or third-party IP to the PowerPC APU interface.

Errata for Virtex®-4 XC4VFX20, XC4VFX40, XC4VFX60, XC4VFX100, and XC4VFX140 production devices.

These errata apply to the Virtex™-4 LX, SX, and FX devices listed within this document.

Errata for Virtex™-4 XC4VFX20CES4S, XC4VFX60CES4S, and XC4VFX100CES4S Devices.

Errata for the Virtex™-4 XC4VLX15CES devices.

Errata for the Virtex™-4 XC4VLX25CES devices.

Errata for the Virtex™-4 XC4VLX40CES devices.

Errata for the Virtex™-4 XC4VLX60CES devices.

Errata for the Virtex™-4 XC4VLX80CES devices.

Errata for the Virtex™-4 XC4VLX100CES devices.

Errata for the Virtex™-4 XC4VLX160CES and XC4VLX200CES devices.

Errata for the Virtex™-4 XC4VSX25CES devices.

Errata for the Virtex™-4 XC4VSX35CES devices.

Errata for the Virtex™-4 XC4VSX55CES devices.

Errata for the Virtex-4 XC4VFX12CES devices.

Errata for the Virtex™-4 XC4VFX20CES2 and XC4VFX60CES2 devices.

Errata for the XC4VFX20CES4, XC4VFX60CES4, XC4VFX100CES4, and XC4VFX140CES4 devices.

Xilinx is changing from a 6 dot HIC to a 3 dot HIC to comply with industry standard dry packing requirements, JEDEC standard J-STD-033.

A new thermal lid adhesive has been qualified for use on all flip-chip packages. The adhesion and thermal properties of the new material are comparable or better than the current thermal and lid attach adhesive.

Xilinx will be using the Stepping Methodology to enhance production offerings. The Virtex™-4 LX and SX families will be the first families to leverage the Stepping Methodology.

A package change in the XC4VLX60 FF1148 production devices.

Starting in 2005, Xilinx Corporation will begin shipping devices manufactured on a 90 nm process from Toshiba, giving Xilinx increased capacity to support Virtex-4 LX production devices.

Xilinx is implementing a Warehouse Management System (WMS) in its internal warehouses worldwide. As a result, a license plate number (LPN), which is a unique tracking number, will now appear on labels beginning in August 2007. There are no changes to the form, fit, or function of the product.

The purpose of this notice is to communicate an increase of Shift Register delay for Virtex™-4 FX devices. This change applies to all Virtex-4 FX devices in -11 and -12 speed grades, except for FX12, and only affects designs that use the Shift Register.

This notice is to inform Virtex™-4 FX users of a revision to the PowerPC™ operating frequency for designs using the APU Controller.

The purpose of this notification is to announce qualification of new second source construction materials, and the addition of a second source supplier for Xilinx plastic flip-chip products. In addition, a mask set stepping introduction for select Virtex®-4 FX products.

Design File(s):

• Qualification Report for XCN07017
• Amkor Qualification Report for XCN07017
• Fujitsu Qualification Report for XCN07017

To communicate that Xilinx is discontinuing certain Development Systems Products.

This notice is to communicate that Xilinx is discontinuing certain Development Systems Products.

To communicate that Xilinx is discontinuing certain Development Systems Products.

To announce conversion of substrate material changed from BT to ABF build-up for select Virtex®-II Pro FPGA and Virtex®-4 FPGA device/package.

To inform Xilinx customers of the removal of Xilinx support for Parity Checking for PowerPC®405 in all Virtex®-4 FX FPGAs for the "XC" Commercial "C", Industrial "I", and Aerospace/Defense "XQ" devices.

To announce conversion of substrate material changed from BT to ABF build-up for select Virtex®-II Pro FPGA device/package.

To communicate that Xilinx is modifying the offerings associated with these LogiCORE™ IP products.

The purpose of this notification is to communicate that Xilinx is discontinuing certain XC3000, XC4000XL, XC5206, Virtex®, Spartan®-3 products, and Aerospace & Defense "XQ" products.

To communicate the discontinuance of the FF676 and FFG676 packages of the Virtex®-4 LX25 FPGA devices.

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To communicate that Xilinx is discontinuing certain Development Systems products - LogiCORE™, IEEE 802 Compatible Viterbi Decoder, University Platform Cable USB-II LeadFree, University Parallel Download Cable and Xilinx Development Systems Products on While Supplies Last.

To communicate that Xilinx is discontinuing certain Development Systems products.

To communicate that Xilinx is discontinuing certain Development Systems products.

To communicate that Xilinx is discontinuing certain Development Systems products.

To communicate an addition of a new supply source for Virtex®-4 and Virtex®-5 FPGA flip chip package build up layers

To communicate that Xilinx is discontinuing certain Development Systems Products.

This notification is to communicate that Xilinx is discontinuing certain Development Systems products.

This notification is to inform Xilinx customers of the consolidation of Virtex®-4 and Virtex®-5 FPGA products at UMC Fab 12 in Tainan, Taiwan.

This notification is to inform Xilinx customers of the discontinuation of certain Virtex®-4 and Virtex®-5 FPGA devices special part numbers only.

To communicate that Xilinx is discontinuing certain Development Systems products

This application note describes the implementation of a Virtex™-4 RocketIO bit-error rate tester (XBERT) reference design. The XBERT reference design generates and verifies non-encoded or 8B/10B-encoded high-speed serial data on one or multiple point-to-point links between Virtex-4 RocketIO Multi-Gigabit Transceiver (MGT) ports embedded within a single Virtex-4 FPGA.

Design File(s):

• xapp713.zip

This application note describes a CIO DDR RLDRAM II controller design implemented in a Virtex®-4 device.

This application note compares the performance between software and hardware implementations of an LPM algorithm. It shows how the hardware implementation, which uses the APU interface of Virtex®-4 FPGAs, outperforms the software implementations.

Design File(s):

• xapp738.zip

Even after volume shipments have begun, customers can take advantage of the "In-System ECO" (Engineering Change Orders) capability in Virtex™-4 EasyPath FPGAs to make changes to LUTs and I/Os. This application note describes how to make these changes in a simple way using the FPGA Editor tool.

This document provides an overview of all Xilinx memory interface application notes that support Virtex™ Series FPGAs. In addition, some key features of the prevalent memory technologies are also provided. For each application note, the data capture technique, clocking scheme, FPGA resources used, and supported memory technology are described briefly.

This application note shows the connection of Xilinx® FPGAs to a Texas Instruments™ S320C6000 series Digital Signal Processor (DSP) using the available External Memory Interface (EMIF).

Design File(s):

• xapp753.zip

UltraController-II is a minimal footprint embedded processing engine based on the PowerPC™ 405 (PPC405) processor core embedded within Virtex™-4 and Virtex-II Pro Platform FPGAs. System designers can easily incorporate the UltraController-II black-box processing engine into larger ISE designs to gain additional degrees of freedom by balancing usage of the high-performance FPGA fabric with the algorithmic flexibility of software.

Describes how to implement a Virtex™-4 FX PowerPC™ 405 system with the Xilinx floating point unit (FPU) coprocessor.

Design File(s):

• xapp547.zip
• xapp547.zip

This book-length compendium of Virtex®-II Pro and Virtex-4 audio and video connectivity solutions for the broadcast industry contains the latest updated revisions of previously published serial video application notes as well as new designs not previously released. See the Preface for a list of the original application note numbers this volume replaces.

Design File(s):

• xapp514.zip

This application note describes a reference design used to bridge one four-channel Xilinx SPI-4.2(PL4) core (v8.1) to four single-channel SPI-3 (PL3) Link Layer cores (v4.1), implemented in a single Virtex™-4 device.

Design File(s):

• xapp737.zip

This document contains detailed information related to the Virtex™-4 RocketIO™ Multi-Gigabit Transceiver (MGT) Static Operating Behavior described in EN014 (Errata for Virtex-4 FX CES2 and CES3 devices) and EN042 (Errata for Virtex-4 CES4 devices).

This application note describes a Redundant Array of Independent Disks (RAID) which is a hard-disk drive (HDD) array where part of the physical storage capacity stores redundant information. Data is regenerated from the physical storage if one or more of the disks in the array (including a single failed disk sector)or the access path to it fails.

Design File(s):

• xapp731.zip

This application note describes techniques for remote reconfiguration of FPGAs through an Ethernet port.

Design File(s):

• xapp441_designfiles.zip
• xapp441_designfiles.zip

This application note details an embedded system example design of a web server running on a PowerPC™ core within a Xilinx Virtex™-4 FPGA. The system is designed using the Embedded Development Kit (EDK). The application note also explains how to set up a system as a web client and how to connect to the web server running on the PowerPC processor.

Design File(s):

• xapp434.zip
• xapp434.zip

This application note details an embedded system example design of a Web server running on the MicroBlaze™ soft processor, designed using the Embedded Development Kit (EDK). The application note also explains how to set up a system as a Web client and how to connect to the Web server running on the MicroBlaze processor.

Design File(s):

• xapp433.zip
• xapp433.zip

Hot-swapping or hot insertion describes a potentially dangerous method of inserting an unpowered board into a power-on (hot) running system. There are several concerns: the insertion must not cause physical harm or permanent damage to the system or the inserted board, and the insertion must not cause data corruption or any transient system upsets. This application note describes the physical aspects of hot-inserting a Virtex™-II based card into a system or system backplane, using sequenced connectors, where VCC and GND mate well before any signal pins can mate. The dangers of using normal non-sequenced connectors are described in Hot Plug-In. Not addressed in this application note are system issues including detecting the presence or absence of a card, or how the card is accepted in the system.

This is a reference system for the OPB IIC on the ML402 Evaluation Platform.

Design File(s):

• xapp982.zip

This describes how to use Create IP Wizard to create custom IP and how to then use it in EDK.

Design File(s):

• xapp967.zip

This application note describes how to build a reference system using the OPB PCI Core on the ML410.

Design File(s):

• xapp964.zip

On-die termination (ODT) promises higher signaling rates for printed circuit board (PCB) inter-chip interfaces through improved signal integrity. However, when using ODT, there is sometimes an associated power penalty. This application note explains the reason for the power penalty and suggests a simulation technique for comparing the signal integrity and power dissipation of internally and externally terminated versions of an interface.

Design File(s):

• xapp863.zip

This application note describes a reference system illustrating how to build an embedded PowerPC™ system using the Virtex™-4 PLB Tri-Mode Ethernet Media Access Controller(PLB_TEMAC).

Design File(s):

• xapp941.zip

This application note discusses dynamic bus mode reconfiguration of PCI-X designs using LogiCORE™ solutions. It shows how to dynamically reload a Virtex™-4 and Virtex-5 FPGA after power-up using a CPLD to dynamically reconfigure the FPGA supporting PCI-X and PCI compatibility.

Design File(s):

• xapp938.zip

This application note focuses on the baseband demodulation of Quadrature Amplitude Modulation (QAM) signals and, more specifically, on the use of a fractional rate decimator block. This application note also reviews polyphase decimating filter architectures and discusses the fractional rate decimator, its Xilinx System Generator 8.1i implementation, and its results.

Design File(s):

• xapp936.zip

This application note provides information on using the PLB DDR2 with OPB Central DMA.

Design File(s):

• xapp935.zip

This document presents design techniques and reference circuits that power Virtex™-4 FX RocketIO™ multi-gigabit transceivers (MGTs) operating at data rates below 3.125 Gb/s.

This application note shows how the 32-bit MicroBlaze™ processor can easily access wide data width memories. The design is also suitable for use with the IBM PowerPC™ (PPC405) processor because it connects to the On-chip Peripheral Bus (OPB). The reference design provides a modification to an existing Xilinx EDK SDRAM interface, enabling a 32-bit processor to access a 64-bit data bus.

Design File(s):

• xapp729.zip

Provides an overview of the baseband processing of a typical W-CDMA base station, along with the associated implementation challenges faced by W-CDMA equipment manufacturers, including the silicon cost, flexibility, and scalability trade-offs.

This application note describes a 267 MHz (and above) DDR2 controller implementation in a Virtex™-4 device interfacing to a Micron DDR2 SDRAM device.

This application note describes the embedded PowerPC™ 405 (PPC405) processor in the Virtex™-4 FX FPGA and the main features of an APU-enhanced system. It includes examples illustrating the APU transfers data between the processor and the FPGA.

Design File(s):

• xapp717.zip

In this application note, the triple error correcting Reed-Muller (RM) is implemented in both the Virtex™-II Pro and Virtex-4 Platform FPGA families.

Design File(s):

• xapp715.zip

This application note describes a DDR SDRAM controller implemented in a Virtex™-4 XC4VLX25 FF668 -10 device. This implementation uses direct clocking for data capture and an automatic calibration circuit to adjust delay on the data lines.

This application note describes the implementation details of a bridge between a 133-MHz, 64-bit PCI-X interface and a 128 MB Double Data Rate (DDR), Small-Outline Dual Inline Memory Module (SODIMM) interface for Virtex™-4 devices. The reference design is capable of reading and writing up to four KB bursts of 64-bit data at 133 MHz.

Design File(s):

• xapp708.zip

Virtex™-4 ChipSync™ technology enables designers to create a wide variety of memory and networking applications. This document provides additional details on the ChipSync operation that are not covered in UG070: Virtex-4 UserGuide.

The full throughput of a Virtex™-4 DSP48 slice can be achieved by time-multiplexing two data streams with a double data rate (DDR) technique. Alpha blending is an example of this technique. This application note describes an alpha blending reference design.

Design File(s):

• xapp706.zip

This application note describes the implementation and timing details of a four-word burst QDR II SRAM interface for Virtex®-4 devices. The synthesizable reference design leverages the unique I/O and clocking capabilities of the Virtex-4 family to achieve performance levels up to 300 MHz (600 Mb/s), resulting in an aggregate throughput for each 36-bit memory interface of 43.2 Gb/s.

This application note demonstrates the use of the On-Chip Peripheral Bus (OPB) External Peripheral Controller (EPC) to support the Cypress CY7C67300 USB controller in a PowerPC™ 405 processor based reference system.

Design File(s):

• xapp925.zip

This application note discusses the use of Partitions in the Incremental Design Flow. It is recommended that module instances with high logic density, timing critical paths, or timing critical module instances be designated Partitions.

This application note describes how C-to-HDL tools can easily create a hardware coprocessor from a critical function in the software system. The Auxiliary Processor Unit (APU) controller closely couples the embedded PowerPC™ processor and the Fabric Coprocessor Module (FCM), and provides a low-latency, high-bandwidth communication path. This application note demonstrates an accelerated Mandelbrot image generation application by moving computation-intensive functions to the hardware domain and attaching it to the PowerPC processor using the Virtex™-4 FX APU controller.

Design File(s):

• xapp901.zip

Describes the Tri-Mode Ethernet MAC (TEMEC) UltraController-II module, which is a minimal footprint, embedded network processing engine based on the PowerPC™ 405 processor core and the TEMAC core embedded within a Virtex™-4 Platform FPGA.

Design File(s):

• xapp807.zip

This application note describes the implementation of a two-dimensional Rank Order filter. The reference design includes the RTL VHDL implementation of an efficient sorting algorithm.

Design File(s):

• xapp953.zip

This application note describes a system for accelerating BER measurements.

Design File(s):

• xapp948.zip

This application note describes a 267-MHz DDR2 controller implementation in a Virtex™-4 device interfacing to a Micron DDR2 SDRAM device.

This application note describes the DDR2 SDRAM physical layer design using the direct-clocking technique in a Virtex™-4 device. The direct-clocking technique utilizes some of the architectural features unique to the Virtex-4 family, for example, the 64-tap absolute delay line provided in each I/O block (IOB).

Describes the 3.3V PCI solution for the Virtex®-II Pro, Virtex-4, and Virtex-5 FPGA families.

This application note describes how to connect Virtex™-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan™-3, and Spartan-3E devices to 3.3V or 5V PCI buses. The design responds to customer demand for a general solution for applications with a Virtex-II device and a 5V PCI bus, as well as for applications with a Virtex-II Pro, Virtex-4, Virtex-5, Spartan-3, or Spartan-3E device and a 3.3V or 5V PCI bus.

This application note describes the implementation of an Error Correction Control (ECC) module in a Virtex™-II, Virtex-II Pro, Virtex-4, and Virtex-5 device. The design can detect and correct all single bit errors (in a code word consisting of either 64-bit data and 8 parity bits, or 32-bit data and 7 parity bits), and it can detect double bit errors in the data. This design utilizes Hamming code, a simple yet powerful method for ECC operations. As a result, this design offers exceptional performance and resource utilization.

Design File(s):

• xapp645.zip
• xapp645.zip

This application note provides step-by-step instructions on how to recreate a Tri-Mode Ethernet (TEMAC) performance testing system using the ML405 board and MontaVista Linux 4.0.

Design File(s):

• xapp1023.zip

This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.

Design File(s):

• xapp1002.zip

This application note describes the steps for using the different clocking resources on the XtremeDSP™ Development Kits developed by Nallatech.

Design File(s):

• xapp1005.zip

This application note describes difference-based partial reconfiguration. This type of reconfiguration is used when making small changes to design parameters including logic equations, filter parameters, and I/O standards.

The ITU-G.709 standard for error correction is examined and implemented in both the Virtex™-4 and Virtex-5 Platform FPGA families using the LogiCORE™ Reed-Solomon (RS) Encoder and Decoder cores.

Design File(s):

• xapp952.zip

This application note describes how to interface 3.3V differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) drivers with Xilinx® 2.5V differential receivers, including Virtex®-II Pro, Virtex-II Pro X, Virtex-4, Virtex-5, Spartan®-3E, and Spartan-3 FPGA 2.5V LVPECL and Low Voltage Differential Signaling (LVDS). Several interface modifications are presented with supporting IBIS simulation results.

This document details the design aspects of digital PLLs implemented in Virtex® and Spartan® FPGAs for telecommunications applications. PLL performance and loop stability are evaluated.

Design File(s):

• xapp868.zip

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

Design File(s):

• xapp058.zip

This application note provides an overview of the architecture and function of avionics full-duplex switched Ethernet (AFDX) as defined in the ARINC Specification 664, Part 7. It also describes how to map various functional blocks required for an AFDX end system to the Virtex®-4 and Virtex-5 architectures.

This Application Note describes a data capture technique for a high-performance DDR2 SDRAM interface. This technique uses the Input Serializer/Deserializer (ISERDES) and Output Serializer/Deserializer (OSERDES) features available in every Virtex™-4 I/O. This technique can be used for memory interfaces with frequencies of 267MHz (533Mb/s) and above.

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

Design File(s):

• xapp502.zip

This application note describes the use of configuration scrubbing and readback in the Virtex®-4 family of FPGAs for detecting and correcting single-event effects induced by cosmic rays.

Design File(s):

• xapp1088.zip

This application note describes the implementation of a YCrCb color space to an RGB Color space conversion circuit necessary in many video designs.

Design File(s):

• xapp931.zip

This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with all Xilinx solutions for PCI Express®.

Design File(s):

• xapp1022.zip

This application note describes a cost-optimized copy protection scheme that helps protect an FPGA against cloning. The design leverages an external secure serial EEPROM. The included reference design uses an optimized PicoBlaze™ 8-bit microcontroller. This application note provides a hardware design with associated PicoBlaze software code. The code loads a secret key into the secure EEPROM and authenticates the user system with the secure EEPROM.

Design File(s):

• xapp780.zip

The OPB USB 2.0 Device core performs the functionality of a USB high speed device and is compliant with the USB 2.0 Specification.

Design File(s):

• xapp997.zip

This application note describes the implementation of six circuits necessary to perform commonly used conversions between various chroma formats. It is accompanied by reference designs which include Generic RTL VHDL code.

Design File(s):

• xapp932.zip

This application note explains how to use the Viterbi Decoder LogiCORE™ module (version 5.0 or later) to implement both trellis termination and tail biting.

Design File(s):

• xapp551.zip

This application note describes how to interface a Texas Instruments analog-to-digital converter (ADC) with serial low-voltage differential signaling (LVDS) outputs to Virtex®-4 or Virtex-5 FPGAs, utilizing the dedicated deserializer functions of both FPGA families.

Design File(s):

• xapp866.zip

Design File(s):

• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

This characterization report provides design verification and characterization results for Virtex™-4 FX RocketIO™ Multi-Gigabit Transceivers (MGTs) using process, voltage, and temperature (PVT) conditions.

Custom DSP algorithms are best modeled mathematically using MATLAB®, while complete systems are best modeled cycle-accurately using Simulink. The marriage of these two modeling domains provides an efficient means to design DSP systems into FPGAs.

This white paper reviews the potential inaccuracies associated with the traditional one-resistor approach to selecting heatsinks, and suggests a more accurate two-resistor (2-R) approach based on both theta-jc and theta-jb from the device datasheet.

This paper focuses on how Xilinx Platform Flash PROMs simplify FPGA configuration design for system and board designers.

Describes Negative-Bias Temperature Instability (NTBI), an unwanted transistor behavior that is pervasive in all deep sub-micron designs.

This paper shows the level of performance that can be reached using Virtex™-4 FPGAs.

This white paper describes design techniques that improve signal integrity in Xilinx® FPGAs.

This paper describes the synthesis and implementation tools strategies, such as Xplorer™, that can be employed to maximize design performance in actual designs with a detailed user constraints file (UCF) or benchmark designs where the user is evaluating the best achievable performance for a specified clock domain.

This white paper discusses the various memory interface controller design challenges and Xilinx solutions, including how to use the Xilinx software tools and hardware-verified reference designs to build a complete memory interface solution for your own application, from low-cost DDR SDRAM applications to higher-performance interfaces like the 667Mb/s DDR2 SDRAMs.

A carefully designed Traffic Manager solution can be scaled and tailored to exactly match the needs of the customer in terms of logic; the customer only pays for the silicon needed. Hence, FPGAs provide the most cost-effective and high-performance solution in this market. Xilinx FPGAs provide the best solution.

This document provides a concise overview of the subset of the MATLAB language, including operators, as well as built-in and toolbox functions supported by AccelDSP™ Synthesis Tool for algorithmic synthesis targeting Xilinx FPGAs.

Considerable effort has been taken into reducing static power in the Virtex™-4 FPGAs. To this end, it is important to consider a realistic FPGA operating temperature.

This paper discusses the overall purpose of OFFSET constraints, the specific paths that are covered by OFFSET constraints, and the differences between the OFFSET IN and OFFSET OUT constraints.

Describes RPR as a network, explains how the MAC operates to provide required network functionality, gives a high-level view of the Virtex™-4 implementation of the MAC, including device sizing, and covers a few system design use cases.

This document focuses on creating HDL code that maps efficiently onto the targeted device. The paper presents coding styles and tips to accelerate design performance. Proper FPGA coding practices are reiterated, and the lesser known techniques directly applicable to the latest Xilinx FPGA architectures are presented.

The M2C-Accelerator extends the Xilinx AccelDSP™ Model-Based Design solution by converting floating-point MATLAB to fixed-point C++ for accelerated MBD verification eliminating a potential bottleneck.

AccelDSP™ Synthesis Tool with IP-Explorer technology eliminates the trial-and-error from using IP blocks by allowing the tool automatically to select from various macro-architectures.

The Physical Synthesis and Optimization tools in the Xilinx ISE software have been created to reexamine the structure of your FPGA design during the packing and placement phases of implementation.

This white paper discusses performance versus power consumption in 90 nm FPGAs and how the Virtex™-4 family provides the best of both worlds: high performance and low power consumption.

This white paper examines alternate uses of available block RAM in Virtex® and Spartan® FPGAs.

This white paper examines how to remove the DC content from a digitally sampled waveform using DSP without complicated mathematics.

This white paper explores the factors of PCI Express® technology and how they affect the performance of a system. This document also provides performance results from two systems that use the Xilinx® Endpoint Block Plus Wrapper for PCI Express in the Virtex®-5 FPGA Integrated Endpoint Block for PCI Express designs.

This white paper describes the steps necessary to analyze your design's power requirements using the Xilinx® Power Estimator.

This white paper describes a rarely noticed design technique that can make a difference in the size and the performance of your FPGA design. Control signals on FPGA flip-flops have a built-in priority. If you can learn to write code that is sympathetic to the priorities, the results will be rewarding. This white paper provides some simple VHDL and Verilog examples to explain key points.

This white paper gives an overall view of the various mainstream digital television standards and outlines related Forward Error Correction solutions available from Xilinx for cable, satellite, terrestrial, and mobile systems.

This white paper examines the causes of jitter, jitter measurement techniques, and methods of managing jitter in digital systems.

This white paper defines IBIS models and describes how to use them to model I/O characteristics for Xilinx® FPGAs.

This white paper defines the use and limitations of bit error ratio measurements when analyzing the performance of communications links.

This white paper discusses signal analysis requirements and methods for printed circuit board design for Xilinx® FPGAs.

This white paper provides a high-level overview of RTCA DO-254 and EUROCAE ED-80 and discusses how Xilinx can assist designers of avionics systems to achieve certification.

This white paper covers the different kinds of IIR filters and structures, and, with the use of The MathWorks® tools, shows how these structures can be mapped to the Xilinx® FPGA architecture.

This document explains the operation of the SPI-4.2 Dynamic Phase Alignment (DPA) Sink Core for Virtex®-4, Virtex-5, Virtex-6, and 7 series FPGAs and provides the guidelines on how to use the SPI-4.2 DPA solution.

This white paper addresses the flexible partial reconfiguration options when designing with 7 series, Virtex®-6, Virtex-5, and Virtex-4 FPGAs.

Modern CMOS processes with their smaller geometries cause certain undesirable side effects. These issues are reviewed with respect to their effect on system design using ASSP, ASIC, or FPGA devices, and what Xilinx has done to alleviate the potential problem.

This white paper updates the results from the 2005 Xilinx Rosetta experiments published in IEEE Transactions on Device and Materials Reliability, clarifies some open issues, and presents additional results for 90 nm and 65 nm technology nodes.

The ability to control system failure modes through fault-tolerant design requires an implementation methodology that ensures fault propagation can be controlled. Xilinx® Isolation Design Flow (IDF) provides fault containment at the FPGA module level, enabling single-chip fault tolerance by various techniques.

The SDI demonstration shows the capabilities of the SDI input and output interfaces on the Video Input and Output Daughter Card (VIODC). The demo can transmit and receive various digital video formats, both high-definition (HD) and standard-definition (SD) using the SDI receiver and transmitter on the VIODC. (The VSK is a demonstration platform only.)

This guide describes VIODC Verilog loop-through demo designs, how to make them, and how to run them. These designs serve as starting points for creating stand-alone VIODC applications using Verilog. The guide also describes how PicoBlaze™ is used to initialize the I2C interface on each device.

This Quick Start Guide provides a brief overview of the content of the kit and describes the installation of the Xilinx software components that are provided with the Video Starter Kit. This document details how to connect your Video Starter Kit to run a first set of diagnostics.

This user guide provides detailed information specific to the Video Input and Output Daughter Card, its video hardware interfaces, and the image sensor camera.

Design File(s):

• viodc_layout.pdf
• viodc_schematic.pdf

This document details the implementation and use of the MPEG-4 Part 2 Decoder Demonstration system that is included with the Video Starter Kit. The design can be used as a demonstration of an FPGA performing video decompression or as a development platform for those interested in building their own systems.

This user guide provides detailed information regarding the kit specifications, software environment using System Generator, supported features, and System Generator-based design examples.

This user guide describes features and operations of the ML405 Evaluation Platform. This board allows users to investigate and experiment with features of the Virtex™-4 FX (XC4VFX20-FF672) FPGA.

Design File(s):

• ML405 Evaluation Platform Documentation

This guide provides user information on determining the optimal DCM phase shift for the DDR feedback clock.

Design File(s):

• ml403_dcm_phase_shift.zip

The Xilinx 19-inch 1U Rack-Mount Chassis along with a Xilinx ML310 or ML410 embedded development platform is intended to be installed into a 4-post network rack for remote use, regression testing or computing and networking clusters. Custom Personality Modules (providing access to the Xilinx RocketIO™ MGTs, SelectIO™ signals, and other resources) a CD-ROM, or a hard disk can be added to the ML310/ML410 board within the Rack-Mount Chassis.

The XGI SuperClock Module User Guide provides an overview of functionality, operation, and configuration of the SuperClock module add-on board.

Describes the components and operation of the ML450 Bit Error Rate Tester (BERT) and its graphical user interface (GUI).

This document describes the features and operation of the ML42x series of RocketIO™ characterization platforms based on Virtex®-4 FX FPGAs.

This manual accompanies the ML410 series of Embedded Development Platforms and contains information about the ML410 hardware and software tools. The ML410 offers designers a versatile Virtex®-4 FX platform for rapid prototyping and system verification.

Design File(s):

• ML410 Embedded Development Platform Documentation
• Reference Designs

User Guide for the Virtex™-4 ML455 PCI/PCI-X Development Kit.

This user guide documents the ML40x reference designs, covering MicroBlaze™ processor based systems for ML401, ML402, and ML403 boards, and PowerPC™ 405 processor based systems for the ML403 and ML405 boards.

This user guide describes features and operation of the ML401 (LX), ML402 (SX), and ML403 (FX) Evaluation Platforms. These boards allow designers to investigate and experiment with the features of the Virtex™-4 family of FPGAs.

Design File(s):

• ML403 Evaluation Platform Documentation

This user guide describes the features and operation of the Virtex™-4 Socketed Development Platforms. These socketed boards can host Virtex-4 LX/SX devices in different packages and speed grades. Extension of all available I/Os to the boards’ “Pin Breakout Area” provide easy probing and analysis of the FPGA under test.

User Guide for the Virtex™-4 ML450 Development Board.

Getting Started with the Virtex®-4 ML403 Board and ISE® and EDK software setup and registration instructions.

This notice is to communicate that Xilinx is discontinuing certain Development Systems Products.

To communicate that Xilinx is discontinuing certain Development Systems Products.

The Virtex®-4 ML461 Memory Interfaces Tool Kit provides a complete development platform to interface with external memory devices for designing and verifying applications based on the Virtex®-4 LX FPGA family.

Design File(s):

• ML461 MIG Reference Design Files

This tutorial helps you get started using the ML401/ML402/ML403/ML405 evaluation platforms. These boards come with a number of pre-installed demonstration programs. This document guides you through these demonstrations and explains how to run them.

Design File(s):

• ML402 Reference Designs
• ML403 Reference Designs

To communicate that Xilinx is discontinuing certain Development Systems Products.