XAPP713 - Virtex-4 RocketIO Bit-Error Rate Tester (PDF)
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This application note describes the implementation of a Virtex™-4 RocketIO bit-error rate tester (XBERT) reference design. The XBERT reference design generates and verifies non-encoded or 8B/10B-encoded high-speed serial data on one or multiple point-to-point links between Virtex-4 RocketIO Multi-Gigabit Transceiver (MGT) ports embedded within a single Virtex-4 FPGA.
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1.1 |
693 KB |
04/18/2007 |
XAPP710 - Synthesizable CIO DDR RLDRAM II Controller for Virtex-4 FPGAs (PDF)
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This application note describes a CIO DDR RLDRAM II controller design implemented in a Virtex®-4 device. Was this document helpful? Yes | No
|
1.4 |
271 KB |
04/28/2008 |
XAPP738 - Code Acceleration with an APU Coprocessor: a Case Study of an LPM Algorithm (PDF)
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This application note compares the performance between software and hardware implementations of an LPM algorithm. It shows how the hardware implementation, which uses the APU interface of Virtex®-4 FPGAs, outperforms the software implementations.
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1.0 |
386 KB |
02/22/2008 |
XAPP803 - Leveraging "In-System ECO" Capability of Virtex-4 EasyPath FPGAs (PDF)
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Even after volume shipments have begun, customers can take advantage of the "In-System ECO" (Engineering Change Orders) capability in Virtex™-4 EasyPath FPGAs to make changes to LUTs and I/Os. This application note describes how to make these changes in a simple way using the FPGA Editor tool. Was this document helpful? Yes | No
|
1.1 |
157 KB |
07/18/2006 |
XAPP802 - Memory Interface Application Notes Overview (PDF)
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This document provides an overview of all Xilinx memory interface application notes that support Virtex™ Series FPGAs. In addition, some key features of the prevalent memory technologies are also provided. For each application note, the data capture technique, clocking scheme, FPGA resources used, and supported memory technology are described briefly. Was this document helpful? Yes | No
|
1.9 |
301 KB |
03/26/2007 |
XAPP780 - FPGA IFF Copy Protection Using Dallas Semiconductor/Maxim DS2432 Secure EEPROMs (PDF)
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This application note describes a cost-optimized copy protection scheme that helps protect an FPGA against cloning. The design leverages an external secure serial EEPROM. The included reference design uses an optimized PicoBlaze™ 8-bit microcontroller. This application note provides a hardware design with associated PicoBlaze software code. The code loads a secret key into the secure EEPROM and authenticates the user system with the secure EEPROM.
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1.0 |
114 KB |
08/17/2005 |
XAPP753 - Interfacing Xilinx FPGAs to TI DSP Platforms Using the EMIF (PDF)
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This application note shows the connection of Xilinx® FPGAs to a Texas Instruments™ S320C6000 series Digital Signal Processor (DSP) using the available External Memory Interface (EMIF).
|
2.0.1 |
1.54 MB |
01/29/2007 |
XAPP575 - UltraController-II: Minimal Footprint Embedded Processing Engine (PDF)
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UltraController-II is a minimal footprint embedded processing engine based on the PowerPC™ 405 (PPC405) processor core embedded within Virtex™-4 and Virtex-II Pro Platform FPGAs. System designers can easily incorporate the UltraController-II black-box processing engine into larger ISE designs to gain additional degrees of freedom by balancing usage of the high-performance FPGA fabric with the algorithmic flexibility of software. Was this document helpful? Yes | No
|
1.1.1 |
953 KB |
08/05/2005 |
XAPP551 - Viterbi Decoder Block Decoding - Trellis Termination and Tail Biting (PDF)
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This application note explains how to use the Xilinx Viterbi Decoder LogiCORE™ module (version 5.0 or later) to implement both trellis termination and tail biting. Was this document helpful? Yes | No
|
1.0 |
139 KB |
02/14/2005 |
XAPP547 - PowerPC Processor with Floating Point Unit for Virtex-4 FX Devices (PDF)
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Describes how to implement a Virtex™-4 FX PowerPC™ 405 system with the Xilinx floating point unit (FPU) coprocessor.
|
1.0.1 |
686 KB |
11/28/2006 |
XAPP514 - Audio/Video Connectivity Solutions for Virtex-II Pro and Virtex-4 FPGAs (PDF)
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This book-length compendium of Virtex®-II Pro and Virtex-4 audio and video connectivity solutions for the broadcast industry contains the latest updated revisions of previously published serial video application notes as well as new designs not previously released. See the Preface for a list of the original application note numbers this volume replaces.
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4.0.1 |
6.22 MB |
10/15/2008 |
XAPP737 - SPI-4.2 to Quad SPI-3 Bridge in Virtex-4 FPGAs (PDF)
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This application note describes a reference design used to bridge one four-channel Xilinx SPI-4.2(PL4) core (v8.1) to four single-channel SPI-3 (PL3) Link Layer cores (v4.1), implemented in a single Virtex™-4 device.
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1.0 |
315 KB |
06/12/2007 |
XAPP732 - Inactive Transceiver Behavior Work-Arounds for Virtex-4 RocketIO MGTs (PDF)
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This document contains detailed information related to the Virtex™-4 RocketIO™ Multi-Gigabit Transceiver (MGT) Static Operating Behavior described in EN014 (Errata for Virtex-4 FX CES2 and CES3 devices) and EN042 (Errata for Virtex-4 CES4 devices). Was this document helpful? Yes | No
|
1.1 |
174 KB |
09/25/2007 |
XAPP731 - Hardware Accelerator for RAID6 Parity (PDF)
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This application note describes a Redundant Array of Independent Disks (RAID) which is a hard-disk drive (HDD) array where part of the physical storage capacity stores redundant information. Data is regenerated from the physical storage if one or more of the disks in the array (including a single failed disk sector)or the access path to it fails.
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1.1 |
681 KB |
03/20/2007 |
XAPP441 - Remote FPGA Reconfiguration Using MicroBlaze or PowerPC (PDF)
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This application note describes techniques for remote reconfiguration of FPGAs through an Ethernet port.
|
1.1 |
480 KB |
09/09/2006 |
XAPP434 - Web Server Reference Design Using a PowerPC-Based Embedded System (PDF)
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This application note details an embedded system example design of a web server running on a PowerPC™ core within a Xilinx Virtex™-4 FPGA. The system is designed using the Embedded Development Kit (EDK). The application note also explains how to set up a system as a web client and how to connect to the web server running on the PowerPC processor.
|
2.2 |
355 KB |
10/13/2006 |
XAPP433 - Embedded System Example: Web Server Design Using MicroBlaze Soft Processor (PDF)
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This application note details an embedded system example design of a Web server running on the MicroBlaze™ soft processor, designed using the Embedded Development Kit (EDK). The application note also explains how to set up a system as a Web client and how to connect to the Web server running on the MicroBlaze processor.
|
2.2 |
269 KB |
10/13/2006 |
XAPP251 - Hot-Swapping Virtex-II, Virtex-II Pro, Virtex-4, and Virtex-5 Devices (PDF)
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Hot-swapping or hot insertion describes a potentially dangerous method of inserting an unpowered board into a power-on (hot) running system. There are several concerns: the insertion must not cause physical harm or permanent damage to the system or the inserted board, and the insertion must not cause data corruption or any transient system upsets. This application note describes the physical aspects of hot-inserting a Virtex™-II based card into a system or system backplane, using sequenced connectors, where VCC and GND mate well before any signal pins can mate. The dangers of using normal non-sequenced connectors are described in Hot Plug-In. Not addressed in this application note are system issues including detecting the presence or absence of a card, or how the card is accepted in the system. Was this document helpful? Yes | No
|
1.3.1 |
125 KB |
05/14/2007 |
XAPP997-Reference Design: Logicore OPB USB 2.0 Device (PDF)
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The OPB USB 2.0 Device core performs the functionality of a USB high speed device and is compliant with the USB 2.0 Specification.
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1.0 |
396 KB |
05/10/2007 |
XAPP982 - Reference System: OPB IIC Using the ML402 Evaluation Platform (PDF)
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1.0 |
755 KB |
03/12/2007 |
XAPP967 - Creating an OPB IPIF-based IP and Using it in EDK (PDF)
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This describes how to use Create IP Wizard to create custom IP and how to then use it in EDK.
|
1.1 |
2.32 MB |
02/26/2007 |
XAPP964 - Reference System: OPB PCI Using the ML410 Embedded Development Platform (PDF)
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This application note describes how to build a reference system using the OPB PCI Core on the ML410.
|
1.1 |
1.94 MB |
01/09/2007 |
XAPP863 - Using Digitally Controlled Impedance: Signal Integrity vs Power Dissipation Considerations (PDF)
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On-die termination (ODT) promises higher signaling rates for printed circuit board (PCB) inter-chip interfaces through improved signal integrity. However, when using ODT, there is sometimes an associated power penalty. This application note explains the reason for the power penalty and suggests a simulation technique for comparing the signal integrity and power dissipation of internally and externally terminated versions of an interface.
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1.0 |
1011 KB |
06/01/2007 |
XAPP941 - Reference System: PLB Tri-Mode Ethernet MAC (PDF)
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This application note describes a reference system illustrating how to build an embedded PowerPC™ system using the Virtex™-4 PLB Tri-Mode Ethernet Media Access Controller(PLB_TEMAC).
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1.1 |
437 KB |
06/15/2007 |
XAPP938 - Dynamic Bus Mode Reconfiguration of PCI-X and PCI Designs Application Note (PDF)
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This application note discusses dynamic bus mode reconfiguration of PCI-X designs using LogiCORE™ solutions. It shows how to dynamically reload a Virtex™-4 and Virtex-5 FPGA after power-up using a CPLD to dynamically reconfigure the FPGA supporting PCI-X and PCI compatibility.
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1.0 |
272 KB |
03/28/2007 |
XAPP936 - Continuously Variable Fractional Rate Decimator (PDF)
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This application note focuses on the baseband demodulation of Quadrature Amplitude Modulation (QAM) signals and, more specifically, on the use of a fractional rate decimator block. This application note also reviews polyphase decimating filter architectures and discusses the fractional rate decimator, its Xilinx System Generator 8.1i implementation, and its results.
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1.1 |
422 KB |
03/05/2007 |
XAPP935 - Reference System: PLB DDR2 with OPB Central DMA (PDF)
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This application note provides information on using the PLB DDR2 with OPB Central DMA.
|
1.1 |
711 KB |
06/07/2007 |
XAPP933 - Two-Dimensional Linear Filtering (PDF)
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This application note provides a Xilinx FPGA solution to two-dimensional filtering with a parameterized VHDL reference design.
|
1.1 |
233 KB |
10/23/2007 |
XAPP932 Chroma Resampler (PDF)
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This application note describes the implementation of six circuits necessary to perform commonly used conversions between various chroma formats.
|
1.0 |
394 KB |
05/09/2006 |
XAPP946 - Switching Power Supplies for Virtex-4 RocketIO MGTs (PDF)
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This document presents design techniques and reference circuits that power Virtex™-4 FX RocketIO™ multi-gigabit transceivers (MGTs) operating at data rates below 3.125 Gb/s. Was this document helpful? Yes | No
|
1.0.1 |
575 KB |
08/14/2006 |
XAPP729 - Interfacing a 64-Bit DDR Memory Bus to a 32-Bit Microprocessor Bus (PDF)
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This application note shows how the 32-bit MicroBlaze™
processor can easily access wide data width memories. The design is also suitable for use with the IBM PowerPC™ (PPC405) processor because it connects to the On-chip Peripheral Bus (OPB). The reference design provides a modification to an existing Xilinx EDK SDRAM
interface, enabling a 32-bit processor to access a 64-bit data bus.
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1.0.1 |
639 KB |
03/04/2007 |
XAPP726 - Benefits of FPGAs in Wireless Base Station Baseband Processing Applications (PDF)
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Provides an overview of the baseband processing of a typical W-CDMA base station, along with the associated implementation challenges faced by W-CDMA equipment manufacturers, including the silicon cost, flexibility, and scalability trade-offs. Was this document helpful? Yes | No
|
1.0 |
250 KB |
07/25/2005 |
XAPP723 - DDR2 Controller (267 MHz and above) Using Virtex-4 Devices (PDF)
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This application note describes a 267 MHz (and above) DDR2 controller implementation in a Virtex™-4 device interfacing to a Micron DDR2 SDRAM device. Was this document helpful? Yes | No
|
1.4 |
332 KB |
10/17/2007 |
XAPP717 - Accelerated System Performance with the APU Controller and XtremeDSP Slices (PDF)
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This application note describes the embedded PowerPC™ 405 (PPC405) processor in the Virtex™-4 FX FPGA and the main features of an APU-enhanced system. It includes examples illustrating the APU transfers data between the processor and the FPGA.
|
1.1.1 |
245 KB |
09/29/2005 |
XAPP715 - Multiple Bit Error Correction (PDF)
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In this application note, the triple error correcting Reed-Muller (RM) is implemented in both the Virtex™-II Pro and Virtex-4 Platform FPGA families.
|
1.0 |
85 KB |
11/15/2004 |
XAPP709 - DDR SDRAM Controller Using Virtex-4 FPGA Devices (PDF)
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This application note describes a DDR SDRAM controller implemented in a Virtex™-4 XC4VLX25 FF668 -10 device. This implementation uses direct clocking for data capture and an automatic calibration circuit to adjust delay on the data lines. Was this document helpful? Yes | No
|
2.0 |
330 KB |
10/27/2006 |
XAPP708 - 133 MHz PCI-X to 128 MB DDR Small-Outline DIMM Memory Bridge (PDF)
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This application note describes the implementation details of a bridge between a 133-MHz, 64-bit PCI-X interface and a 128 MB Double Data Rate (DDR), Small-Outline Dual Inline
Memory Module (SODIMM) interface for Virtex™-4 devices. The reference design is capable of reading and writing up to four KB bursts of 64-bit data at 133 MHz.
|
1.0 |
325 KB |
02/14/2006 |
XAPP707 - Advanced ChipSync Applications (PDF)
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Virtex™-4 ChipSync™ technology enables designers to create a wide variety of memory and networking applications. This document provides additional details on the ChipSync operation that are not covered in UG070: Virtex-4 UserGuide. Was this document helpful? Yes | No
|
1.0 |
1.97 MB |
10/31/2006 |
XAPP706 - Alpha Blending Two Data Streams Using a DSP48 DDR Technique (PDF)
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The full throughput of a Virtex™-4 DSP48 slice can be achieved by time-multiplexing two data streams with a double data rate (DDR) technique. Alpha blending is an example of this technique. This application note describes an alpha blending reference design.
|
1.0 |
479 KB |
03/31/2005 |
XAPP703 - QDR II SRAM Interface for Virtex-4 Devices (PDF)
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This application note describes the implementation and timing details of a four-word burst QDR II SRAM interface for Virtex®-4 devices. The synthesizable reference design leverages the unique I/O and clocking capabilities of the Virtex-4 family to achieve performance levels up to 300 MHz (600 Mb/s), resulting in an aggregate throughput for each 36-bit memory interface of 43.2 Gb/s. Was this document helpful? Yes | No
|
2.4 |
580 KB |
07/09/2008 |
XAPP931 - Color-Space Converter: YCrCb to RGB (PDF)
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This application note describes the implementation of a YCrCb color space to an RGB Color space conversion circuit necessary in many video designs.
|
1.1 |
335 KB |
10/13/2006 |
XAPP930 - Color-Space Converter: RGB to YCrCb (PDF)
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This application note describes the implementation of an RGB color space to a YCbCr color space conversion circuit necessary in many video designs.
|
1.0.1 |
326 KB |
08/27/2007 |
XAPP925 - Reference System: Using the OPB EPC with the Cypress CY7C67300 USB Controller (PDF)
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This application note demonstrates the use of the On-Chip Peripheral Bus (OPB) External Peripheral Controller (EPC) to support the Cypress CY7C67300 USB controller in a PowerPC™ 405 processor based reference system.
|
1.3 |
409 KB |
06/01/2007 |
XAPP918 - Incremental Design Reuse with Partitions (PDF)
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This application note discusses the use of Partitions in the Incremental Design Flow. It is recommended that module instances with high logic density, timing critical paths, or timing critical module instances be designated Partitions. Was this document helpful? Yes | No
|
1.0 |
1.03 MB |
06/07/2007 |
XAPP901 - Accelerating Software Applications Using the APU Controller and C-to-HDL Tools (PDF)
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This application note describes how C-to-HDL tools can easily create a hardware coprocessor from a critical function in the software system. The Auxiliary Processor Unit (APU) controller closely couples the embedded PowerPC™ processor and the Fabric Coprocessor Module (FCM), and provides a low-latency, high-bandwidth communication path. This application note demonstrates an accelerated Mandelbrot image generation application by moving computation-intensive functions to the hardware domain and attaching it to the PowerPC processor using the Virtex™-4 FX APU controller.
|
1.0 |
508 KB |
12/16/2005 |
XAPP866 - An Interface for Texas Instruments Analog-to-Digital Converters with Serial LVDS Outputs (PDF)
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This application note describes how to interface a Texas Instruments analog-to-digital converter (ADC) with serial low-voltage differential signaling (LVDS) outputs to Virtex®-4 or Virtex-5 FPGAs, utilizing the dedicated deserializer functions of both FPGA families.
|
3.0 |
861 KB |
04/07/2008 |
XAPP807 - Minimal Footprint Tri-Mode Ethernet MAC Processing Engine (PDF)
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Describes the Tri-Mode Ethernet MAC (TEMEC) UltraController-II module, which is a minimal footprint, embedded network processing engine based on the PowerPC™ 405 processor core and the TEMAC core embedded within a Virtex™-4 Platform FPGA.
|
1.3 |
576 KB |
01/17/2007 |
XAPP953 - Two-Dimensional Rank Order Filter (PDF)
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This application note describes the implementation of a two-dimensional Rank Order filter. The reference design includes the RTL VHDL implementation of an efficient sorting algorithm.
|
1.1 |
431 KB |
09/21/2006 |
XAPP948 - Hardware Acceleration of 3GPP Turbo Encoder/Decoder BER Measurement Using System Generator (PDF)
|
1.0 |
808 KB |
12/05/2006 |
XAPP702 - DDR2 Controller Using Virtex-4 Devices (PDF)
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This application note describes a 267-MHz DDR2 controller implementation in a Virtex™-4 device interfacing to a Micron DDR2 SDRAM device. Was this document helpful? Yes | No
|
1.8 |
306 KB |
04/23/2007 |
XAPP701 - DDR2 SDRAM Physical Layer Using Direct-Clocking Technique (PDF)
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This application note describes the DDR2 SDRAM physical layer design using the direct-clocking technique in a Virtex™-4 device. The direct-clocking technique utilizes some of the architectural features unique to the Virtex-4 family, for example, the 64-tap absolute delay line provided in each I/O block (IOB). Was this document helpful? Yes | No
|
2.0 |
275 KB |
03/12/2007 |
XAPP653 - 3.3V PCI Design Guidelines (PDF)
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Describes the 3.3V PCI solution for the Virtex®-II Pro, Virtex-4, and Virtex-5 FPGA families. Was this document helpful? Yes | No
|
3.1.1 |
196 KB |
05/12/2008 |
XAPP646 - Connecting Virtex-II Devices to a 3.3V/5V PCI Bus (PDF)
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This application note describes how to connect Virtex™-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan™-3, and Spartan-3E devices to 3.3V or 5V PCI buses. The design responds to customer demand for a general solution for applications with a Virtex-II device and a 5V PCI bus, as well as for applications with a Virtex-II Pro, Virtex-4, Virtex-5, Spartan-3, or Spartan-3E device and a 3.3V or 5V PCI bus. Was this document helpful? Yes | No
|
1.2.2 |
65 KB |
04/23/2007 |
XAPP645 - Single Error Correction and Double Error Detection (PDF)
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This application note describes the implementation of an Error Correction Control (ECC) module in a Virtex™-II, Virtex-II Pro, Virtex-4, and Virtex-5 device. The design can detect and correct all single bit errors (in a code word consisting of either 64-bit data and 8 parity bits, or 32-bit data and 7 parity bits), and it can detect double bit errors in the data. This design utilizes Hamming code, a simple yet powerful method for ECC operations. As a result, this design offers exceptional performance and resource utilization.
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2.2 |
184 KB |
08/09/2006 |
XAPP1023 - Benchmarking the Performance of the Virtex -4 10/100/1000 TEMAC System (PDF)
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This application note provides step-by-step instructions on how to recreate a Tri-Mode Ethernet (TEMAC) performance testing system using the ML405 board and MontaVista Linux 4.0.
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1.0 |
2.3 MB |
10/03/2007 |
XAPP1002 - Using ChipScope Pro to Debug Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE (PDF)
View Document Details
This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI
Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.
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1.0 |
1.27 MB |
10/22/2007 |
XAPP1022 - Using MET with PIO Example Design for PCI Express Endpoint Cores (PDF)
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This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with the Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE for PCI Express® Xilinx solutions.
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1.0 |
1.19 MB |
09/19/2007 |
XAPP1005 - Using Clocking Resources on XtremeDSP Development Kits (PDF)
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This application note describes the steps for using the different clocking resources on the XtremeDSP™ Development Kits developed by Nallatech.
|
1.1 |
1.02 MB |
10/03/2007 |
XAPP290 - Difference-Based Partial Reconfiguration (PDF)
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This application note describes difference-based partial reconfiguration. This type of reconfiguration is used when making small changes to design parameters including logic equations, filter parameters, and I/O standards. Was this document helpful? Yes | No
|
2.0 |
305 KB |
12/03/2007 |
XAPP952 - Forward Error Correction on ITU-G.709 Networks using Reed-Solomon Solutions (PDF)
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The ITU-G.709 standard for error correction is examined and implemented in both the Virtex™-4 and Virtex-5 Platform FPGA families using the LogiCORE™ Reed-Solomon (RS) Encoder and Decoder cores.
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1.0 |
406 KB |
12/05/2007 |
XAPP696 - Interfacing LVPECL 3.3V Drivers with Xilinx 2.5V Differential Receivers (PDF)
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This application note describes how to interface 3.3V differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) drivers with Xilinx® 2.5V differential receivers, including Virtex®-II Pro, Virtex-II Pro X, Virtex-4, Virtex-5, Spartan®-3E, and Spartan-3 FPGA 2.5V LVPECL and Low Voltage Differential Signaling (LVDS). Several interface modifications are presented with supporting IBIS simulation results. Was this document helpful? Yes | No
|
1.3 |
324 KB |
05/01/2008 |
XAPP868 - Clock Data Recovery Design Techniques for E1/T1 Based on Direct Digital Synthesis (PDF)
View Document Details
This document details the design aspects of digital PLLs implemented in Virtex® and Spartan® FPGAs for telecommunications applications. PLL performance and loop stability are evaluated.
|
1.0 |
287 KB |
01/29/2008 |
XAPP058 - Xilinx In-System Programming Using an Embedded Microcontroller (PDF)
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The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.
|
4.1 |
641 KB |
03/06/2009 |
XAPP1130 - Architecting ARINC 664, Part 7 (AFDX) Solutions (PDF)
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This application note provides an overview of the architecture and function of avionics full-duplex switched Ethernet (AFDX) as defined in the ARINC Specification 664, Part 7. It also describes how to map various functional blocks required for an AFDX end system to the Virtex®-4 and Virtex-5 architectures. Was this document helpful? Yes | No
|
1.0.1 |
1.26 MB |
05/22/2009 |
XAPP721 - High-Performance DDR2 SDRAM Interface Data Capture Using ISERDES and OSERDES (PDF)
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This Application Note describes a data capture technique for a high-performance DDR2 SDRAM interface. This technique uses the Input Serializer/Deserializer (ISERDES) and Output Serializer/Deserializer (OSERDES) features available in every Virtex™-4 I/O. This technique can be used for memory interfaces with frequencies of 267MHz (533Mb/s) and above. Was this document helpful? Yes | No
|
2.2 |
397 KB |
07/29/2009 |
XAPP502 - Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode (PDF)
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In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.
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1.6.1 |
356 KB |
08/24/2009 |
XAPP1088 - Correcting Single-Event Upsets in Virtex-4 FPGA Configuration Memory (PDF)
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This application note describes the use of configuration scrubbing and readback in the Virtex®-4 family of FPGAs for detecting and correcting single-event effects induced by cosmic rays.
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1.0 |
589 KB |
10/05/2009 |