Virtex-4QV
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Virtex-4QV FPGA Data Sheets
| Date | Name |
|---|---|
| 04/12/2010 | Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics(PDF, ver 2.0, 286 KB )
This data sheet provides the DC and switching characteristics for the space-grade, radiation-tolerant Virtex®-4QV FPGAs. |
| 04/12/2010 | Space-Grade Virtex-4QV Family Overview(PDF, ver 2.0, 113 KB )
This document provides an overview of the space-grade, radiation-tolerant Virtex®-4QV family. |
topVirtex-4QV FPGA User Guides
| Date | Name |
|---|---|
| 04/02/2008 | Virtex-4 QV FPGA Ceramic Packaging and Pinout Specifications(PDF, ver 1.0, 1.84 MB )
This guide provides complete packing information for Virtex®-4 QPro™-V (QV) Radiation-Hardened FPGAs in 1.00-mm pitch ceramic flip-chip column grid array (CF) packages. Virtex-4 QV Radiation Hardened FPGAs are offered exclusively in ceramic flip-chip column grid array (CF) packages that are optimally designed for improved thermal cycle reliability. Design File(s): |
Virtex-4QV FPGA Customer Notices
| Date | Name |
|---|---|
| 04/19/2010 | XCN10006 - Aerospace and Defense Bumping Supplier Change: Virtex-4QV FPGA Space-Grade Devices Using Ceramic Flip Chip Column Grid Array (CF) Packages (PDF, ver 1.0, 48 KB )
To announce that Xilinx has qualified a new bumping supplier for Virtex®-4QV FPGA space-grade devices in ceramic flip chip column grid array (CF) packages. |
| 12/07/2009 | XCN09033 - Humidity Indicator Card (HIC) Change(PDF, ver 1.0, 67 KB )
To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function. |
Virtex-4QV FPGA Application Notes
| Date | Name |
|---|---|
| 04/02/2008 | XAPP989 - Correcting Single-Event Upsets with a Self-Hosting Configuration Management Core(PDF, ver 1.0, 444 KB )
This application note discusses self-hosting configuration management hardware setup for Xilinx® FPGAs for the purpose of detecting and correcting single-event upsets (SEUs) to the configuration memory array. |
| 03/14/2008 | XAPP962 - Single Event Upset Mitigation for Xilinx FPGA Block Memories(PDF, ver 1.1, 2.48 MB )
This application note describes mitigation techniques using triple-module-redundancy (TMR) combined with configuration scrubbing for Xilinx®-specific block RAMs in high radiation environments. Also included is a design example demonstrating these mitigation techniques. Design File(s): |
| 03/14/2008 | XAPP1004 - Single-Event Upset Mitigation Design Flow for Xilinx FPGA PowerPC Systems(PDF, ver 1.0, 2.08 MB )
This application note describes mitigation techniques and corresponding design flow when using a Xilinx® FPGA with an embedded processor (specifically the PowerPC® 405 found in the Virtex®-4 FX family) in high-radiation environments. Design File(s): |
| 03/18/2008 | XAPP987 - Single-Event Upset Mitigation Selection Guide(PDF, ver 1.0, 335 KB )
This application note discusses different aspects of single-event upsets and recommends appropriate mitigation schemes under each circumstance. |
| 10/05/2009 | XAPP1088 - Correcting Single-Event Upsets in Virtex-4 FPGA Configuration Memory(PDF, ver 1.0, 589 KB )
This application note describes the use of configuration scrubbing and readback in the Virtex®-4 family of FPGAs for detecting and correcting single-event effects induced by cosmic rays. Design File(s): |
Virtex-4QV FPGA Characterization Reports
| Date | Name |
|---|---|
| 04/02/2010 | Qualification Report for XCN10006(PDF, ver 1.0, 194 KB )
Aerospace and Defense Bumping Supplier Change: Virtex®-4QV Space-Grade Devices Using Ceramic Flip-Chip Column Grid, Qualification Report |