Virtex-5

This document is a brief introduction to the features of the Virtex®-5 devices. It contains the device summary, packaging options, and ordering information.

This data sheet specifies the electrical characteristics of the Virtex®-5 family of FPGAs, including absolute maximum ratings, recommended operating conditions, supply requirements, and switching characteristics.

All package files are ASCII files in zip format.

The Virtex®-5 FPGA User Guide includes chapters on clocking resources, clock management technology, phase-locked loops, block RAM, Configurable Logic Blocks (CLBs), SelectIO™ resources, and SelectIO logic resources.

Design File(s):

• ug190_SSO_Calculator.zip

This user guide provides Virtex®-5 device pinouts, package specifications, pinout diagrams, PCB design rules, and thermal data.

This guide describes the System Monitor functionality available in all Virtex®-5 devices.

Design File(s):

• ug192.zip

This user guide describes the dedicated Tri-Mode Ethernet Media Access Controller (MAC) available in Virtex®-5 devices.

This guide describes the functionality of the dedicated Integrated Endpoint block for PCI Express® designs available in the Virtex®-5 LXT, SXT, TXT, and FXT devices.

This all-encompassing configuration guide includes detailed information on the Virtex®-5 FPGA configuration interfaces (JTAG, Serial, SelectMAP, SPI and BPI), and it discusses flows and techniques for bitstream encryption, readback and reconfiguration.

This reference guide describes the embedded processor block available in the Virtex®-5 FXT device.

This document describes the Virtex®-5 FPGA DSP48E slice.

Design File(s):

• ug193.zip

Summary of the reliability test data and results for Xilinx devices updated four times per year.

This guide describes the RocketIO™ GTP transceivers available in the Virtex®-5 LXT and SXT devices.

This guide describes the RocketIO™ GTX transceivers available in the Virtex®-5 TXT and FXT devices.

This guide describes the functionality of the dedicated Integrated Endpoint block for PCI Express® designs available in the Virtex®-5 LXT, SXT, TXT, and FXT devices.

This guide provides information on PCB design for Virtex®-5 devices, with a focus on strategies for making design decisions at the PCB and the interface level.

Errata for Virtex®-5 TXT and FXT FPGAs.

Errata for the following Virtex®-5 devices: XC5VFX30T CES, XC5VFX70T CES, XC5VFX100T CES, XC5VFX130T CES, and XC5VFX200T CES FPGAs

Errata for the following Virtex®-5 devices: XC5VFX30T, XC5VFX70T, XC5VFX100T, XC5VFX130T, and XC5VFX200T CES9988 FPGA

Errata for the following Virtex™-5 ES devices: XC5VLX30CES, XC5VLX50CES, XC5VLX85CES, XC5VLX110CES, XC5VLX220CES, and XC5VLX330CES.

Errata for the following Virtex™-5 LXT devices: XC5VLX30TCES, XC5VLX50TCES, XC5VLX110TCES, and XC5VLX330TCES.

Errata for the following Virtex®-5 SXT devices: XC5VSX35TCES and XC5VSX50TCES.

The purpose of this notification is to communicate a data sheet pin-to-pin specification change for the Virtex™-5 family.

The purpose of this document is to inform the customer of a standardization effort for on-package capacitors used in Virtex®-5 FXT FPGA FF(G)1738 and FF(G)1136 packages for the prefix “XC” Commercial “C” and Industrial “I” devices.

To communicate that Xilinx is discontinuing certain Development Systems Products.

The purpose of this notification is to communicate a 10-layer package substrate change for select Virtex®-5 LX devices.

Design File(s):

• FAQ for XCN07025
• Qualification Report

This notice is to communicate that Xilinx is discontinuing certain Development Systems Products.

The purpose of this notification is to communicate a transition to Step 1 and a 10-layer package substrate for select Virtex®-5 LXT and SXT FPGA devices.

Design File(s):

• FAQ for XCN07026
• Qualification Report

To communicate that Xilinx is discontinuing certain Development Systems Products.

To announce conversion of substrate material changed from BT to ABF build-up for select Virtex®-II Pro FPGA and Virtex®-4 FPGA device/package.

To announce conversion of substrate material changed from BT to ABF build-up for select Virtex®-II Pro FPGA device/package.

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To communicate that Xilinx is discontinuing certain Development Systems products - LogiCORE™, IEEE 802 Compatible Viterbi Decoder, University Platform Cable USB-II LeadFree, University Parallel Download Cable and Xilinx Development Systems Products on While Supplies Last.

To communicate that Xilinx is discontinuing certain Development Systems products.

To communicate that Xilinx is discontinuing certain Development Systems products.

To communicate that Xilinx is discontinuing certain Development Systems products.

To communicate an addition of a new supply source for Virtex®-4 and Virtex®-5 FPGA flip chip package build up layers

To communicate that Xilinx is discontinuing certain Development Systems Products.

To communicate an addition of a new supply source for Virtex®-5 FPGA flip chip BGA package core material and also announce an additional package supplier for Virtex-5 FPGA flip chip BGA package substrates.

This notification is to communicate that Xilinx is discontinuing certain Development Systems products.

This notification is to inform Xilinx customers of the consolidation of Virtex®-4 and Virtex®-5 FPGA products at UMC Fab 12 in Tainan, Taiwan.

This notification is to inform Xilinx customers of the discontinuation of certain Virtex®-4 and Virtex®-5 FPGA devices special part numbers only.

To communicate that Xilinx is discontinuing certain Development Systems products

This application note demonstrates how to run a simulation of an EDK system containing the PLBv46 Endpoint Bridge for PCI Express® core. C code running on the PowerPC® 440 drives the EDK system.

Design File(s):

• Design file for XAPP1111

This application note demonstrates how to run a simulation of an EDK system containing the PLBv46 Endpoint Bridge for PCI Express®.

Design File(s):

• Design file for XAPP1110

This application note describes how to use the Virtex®-5 FPGA input/output delay (IODELAY) primitive as a means to create a high-precision adjustable oscillator with a wide tuning range. Three different use models are described for the adjustable oscillator:

Design File(s):

• xapp872.zip

This application note outlines the techniques for debugging PowerPC® 440 processor systems in hardware and simulation.

Design File(s):

• xapp1060.zip

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

Design File(s):

• xapp058.zip

This application note covers the details (both hardware and software) of setting up successful configuration and reconfiguration of Virtex®-5 FPGAs from Platform Flash XL.

Design File(s):

• xapp1100.zip

This application note provides an overview of the architecture and function of avionics full-duplex switched Ethernet (AFDX) as defined in the ARINC Specification 664, Part 7. It also describes how to map various functional blocks required for an AFDX end system to the Virtex®-4 and Virtex-5 architectures.

The application discusses the use of the Xilinx® Microprocessor Debugger (XMD) and the GNU software debugger (GDB) to debug software defects.

Design File(s):

• xapp1117.zip

This application note provides a reference design for endpoint-initiated Direct Memory Access (DMA) data transfers using the LogiCORE™ Endpoint Block Plus for Virtex®-5 FPGAs.

Design File(s):

• xapp859.zip

This application note discusses Linux Operating System debugging techniques. Debugging boot issues, kernel panics, software and hardware debuggers, driver <-> application interaction, and various other tools are discussed.

Design File(s):

• Design Files for XAPP1137

This application note describes the controller and the data capture technique for high-performance DDR3 SDRAM interfaces. This data capture technique uses the Input Double Data Rate (IDDR) and Output Double Data Rate (ODDR) features available in every Virtex®-5 FPGA I/O.

Design File(s):

• xapp867.zip

Previous generations of Xilinx® FPGAs supported a Master Parallel Configuration Mode which allowed the FPGA to configure itself directly from a parallel (byte wide) PROM. The Virtex® family of Xilinx FPGAs does not utilize a Master Parallel mode. This application note describes a simple interface design to configure a Virtex device from a parallel EPROM using the SelectMAP configuration mode.

Design File(s):

• xapp137.zip

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

Design File(s):

• xapp502.zip

This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with all Xilinx solutions for PCI Express®.

Design File(s):

• xapp1022.zip

This application note describes how to use a Virtex®-5 device to interface to Common I/O(CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices.

Design File(s):

• xapp852.zip

This application note describes the implementation of SerDes Framer Interface Level 4 Phase 2 (SFI4.2) in a Virtex®-5 FPGA XC5VFX70T.

Design File(s):

• xapp877.zip

This Virtex™-5 application note describes an SFI-4.1 interface, a 16-channel, source-synchronous LVDS interface operating at SDR. The transmitter requires 16 LVDS pairs for data and one LVDS pair for the forwarded clock. The receiver also requires 16 LVDS pairs for data and one LVDS pair for the source-synchronous clock input.The timing of the receiver is described in depth and characterized in hardware.

Design File(s):

• xapp856.zip

This application note describes how to indirectly program select BPI PROMs through the JTAG interface of a Virtex®-5 FPGA using iMPACT. The required hardware setup, BPI-UP PROM file generation, and the indirect programming flow are described.

This application note provides a discussion of strategies and representative calculations for handling single event upsets (SEUs) with an emphasis on reliability when addressing these low probability events. This application note also introduces an SEU controller macro that can be included in any Virtex®-5 FPGA design to implement an SEU detection and correction scheme.

This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express® used in the Xilinx ML507 Embedded Development Platform.

Design File(s):

• xapp1040.zip

This application note provides background on NSEUs in SRAM-based FPGAs, mitigation techniques (with a focus on configuration memory) suggested by Xilinx, and an overview of calculating projected failures-in-time (FIT) rates at altitude.

This application note describes the implementation and timing details of a four-word burst Quad Data Rate (QDR II) SRAM interface for Virtex®-5 devices.

This application note describes how to interface a Fujitsu MB86064 digital-to-analog converter (DAC) with parallel low-voltage differential signaling (LVDS) inputs to a Virtex®-5 FPGA utilizing the dedicated I/O functions of the FPGA family.

Design File(s):

• xapp873.zip

This application note demonstrates how to efficiently implement Digitial Up and Down Converters(DUC/DDC) by leveraging the Xilinx® DSP IP portfolio. Two example DUC/DDC designs are provided for UMTS and CDMA2000 in both Spartan®-3A DSP and Virtex®-5 FPGAs.

Design File(s):

• xapp1018_cdma2000.zip
• xapp1018_wcdma.zip

The non-integer data recovery unit (NI-DRU) presented in this application note is specifically designed for RocketIO™ GTP and GTX transceivers in Virtex®-5 LXT, SXT, TXT, and FXT platforms and consists of look-up tables (LUTs) and flip-flops. The NI-DRU extends the lower data rate limit to 0 Mb/s and the upper limit to 1,250 Mb/s, making embedded high-speed transceivers the ideal solution for true multi-rate serial interfaces.

Design File(s):

• xapp875.zip

This application note is a collection of audio and video connectivity solutions for the broadcast industry. It describes how to use Virtex®-5 FPGAs to implement serial digital video and audio interfaces commonly used in the professional video broadcast industry. The associated reference designs support many video rates and standards, and provide for embedded audio.

Design File(s):

• xapp1014.zip

This application note describes the controller and data capture technique for high-performance DDR2 SDRAM interfaces. This data capture technique uses the Input Serializer/Deserializer (ISERDES) and Output Double Data Rate (ODDR) features available in every Virtex®-5 I/O.

This application note describes how to interface a Texas Instruments analog-to-digital converter (ADC) with serial low-voltage differential signaling (LVDS) outputs to Virtex®-4 or Virtex-5 FPGAs, utilizing the dedicated deserializer functions of both FPGA families.

Design File(s):

• xapp866.zip

This application note describes a data integrity controller for partial reconfiguration (PRC) that can be included in any partially reconfigurable FPGA design to process partial bitstreams for data integrity.

Design File(s):

• xapp887_PRC_EPRC.zip

The USR_ACCESS register, present in the Virtex®-5, Virtex-6, and all 7 series FPGAs, provides the ability to embed version information into a 32-bit fabric-accessible register at the bitstream generation phase, allowing for the best balance of flexibility for the user with minimal impact to the design and implementation time.

This application note discusses how to design and implement a Bus Master design using Xilinx® Endpoint PCI Express® solutions. A performance demonstration reference design using Bus Mastering is included with this application note. The reference design can be used to gauge achievable performance in various systems and act as a starting point for an application-specific Bus Master Direct Memory Access (DMA). The reference design includes all files necessary to target the Integrated Blocks for PCI Express on the Virtex®-6 and Spartan®-6 FPGAs, the Endpoint Block Plus Wrapper Core for PCI Express using the Virtex-5 FPGA Integrated Block for PCI Express, and the Endpoint PIPE for PCI Express targeting the Xilinx Spartan®-3 family of devices.

Design File(s):

• xapp1052.zip

This application note describes a system using the Virtex™-5 Embedded Tri-Mode Ethernet MAC (Ethernet MAC) Wrapper core on a Xilinx® Virtex-5 ML505 development board.

Design File(s):

• xapp957.zip

Describes the hardware accelerator for RAID6 parity generation / data recovery controller with ECC and MIG DDR2 controller.

Design File(s):

• xapp865.zip

Hot-swapping or hot insertion describes a potentially dangerous method of inserting an unpowered board into a power-on (hot) running system. There are several concerns: the insertion must not cause physical harm or permanent damage to the system or the inserted board, and the insertion must not cause data corruption or any transient system upsets. This application note describes the physical aspects of hot-inserting a Virtex™-II based card into a system or system backplane, using sequenced connectors, where VCC and GND mate well before any signal pins can mate. The dangers of using normal non-sequenced connectors are described in Hot Plug-In. Not addressed in this application note are system issues including detecting the presence or absence of a card, or how the card is accepted in the system.

On-die termination (ODT) promises higher signaling rates for printed circuit board (PCB) inter-chip interfaces through improved signal integrity. However, when using ODT, there is sometimes an associated power penalty. This application note explains the reason for the power penalty and suggests a simulation technique for comparing the signal integrity and power dissipation of internally and externally terminated versions of an interface.

Design File(s):

• xapp863.zip

Virtex™-5 devices have a high-precision programmable delay element (IDELAY) associated with every input pin. This application note shows how to implement 8X oversampling of many data streams using a single DCM, two global clock resources, and minimal FPGA logic resources. This solution provides better jitter tolerance than techniques using multiple DCMs. When paired with a suitable data recovery scheme, this oversampling technique can be used with many different data protocols up to 550 Mb/s. A reference design is included that implements a SD-SDI (SMPTE 259M) receiver running at 270 Mb/s.

Design File(s):

• xapp861.zip

This application note describes a 16-channel, source-synchronous DDR LVDS interface. The receiver operates at 1:6 deserialization on each of the 16 data channels. Similar to XAPP855, the design also includes a real-time window monitoring circuit for added performance. This reference design calibrates and compensates for skews associated with process, voltage, and temperature (PVT) at initialization and dynamically during operation.

Design File(s):

• xapp860.zip

This application note discusses dynamic bus mode reconfiguration of PCI-X designs using LogiCORE™ solutions. It shows how to dynamically reload a Virtex™-4 and Virtex-5 FPGA after power-up using a CPLD to dynamically reconfigure the FPGA supporting PCI-X and PCI compatibility.

Design File(s):

• xapp938.zip

This application note focuses on the baseband demodulation of Quadrature Amplitude Modulation (QAM) signals and, more specifically, on the use of a fractional rate decimator block. This application note also reviews polyphase decimating filter architectures and discusses the fractional rate decimator, its Xilinx System Generator 8.1i implementation, and its results.

Design File(s):

• xapp936.zip

This application note describes a 16-channel, source-synchronous DDR LVDS interface. The design takes advantage of the Virtex™-5 I/O ChipSync™ features ability to adjust the delay of the receiver datapaths creating dynamic setup/hold timing for each device at initialization, compensating for skews associated with the manufacturing process. The receiver operates at 1:8 deserialization on each of the 16 data channels.

Design File(s):

• xapp855.zip

This application note describes a 200-MHz DDR SDRAM memory controller implemented in a Virtex™-5 device. This reference design uses the Virtex-5 ChipSync features to calibrate and adjust read data timing. A straightforward backend user interface is provided to allow integration into a complete FPGA design.

Design File(s):

• xapp851.zip

This application note discusses the use of Partitions in the Incremental Design Flow. It is recommended that module instances with high logic density, timing critical paths, or timing critical module instances be designated Partitions.

Describes the 3.3V PCI solution for the Virtex®-II Pro, Virtex-4, and Virtex-5 FPGA families.

This application note describes the implementation of an Error Correction Control (ECC) module in a Virtex™-II, Virtex-II Pro, Virtex-4, and Virtex-5 device. The design can detect and correct all single bit errors (in a code word consisting of either 64-bit data and 8 parity bits, or 32-bit data and 7 parity bits), and it can detect double bit errors in the data. This design utilizes Hamming code, a simple yet powerful method for ECC operations. As a result, this design offers exceptional performance and resource utilization.

Design File(s):

• xapp645.zip
• xapp645.zip

This application note provides a reference design for point-to-point (FPGA to FPGA) high-speed serial packet transfer functionality using the integrated Endpoint block for PCI Express® designs in a Virtex™-5 LXT FPGA.

Design File(s):

• xapp869.zip

This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.

Design File(s):

• xapp1002.zip

This application note describes difference-based partial reconfiguration. This type of reconfiguration is used when making small changes to design parameters including logic equations, filter parameters, and I/O standards.

The ITU-G.709 standard for error correction is examined and implemented in both the Virtex™-4 and Virtex-5 Platform FPGA families using the LogiCORE™ Reed-Solomon (RS) Encoder and Decoder cores.

Design File(s):

• xapp952.zip

This application note explains the techniques to support SATA initialization in the GTP transceiver of the Virtex®-5 LXT platform.

Design File(s):

• xapp870.zip

This application note describes how to interface 3.3V differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) drivers with Xilinx® 2.5V differential receivers, including Virtex®-II Pro, Virtex-II Pro X, Virtex-4, Virtex-5, Spartan®-3E, and Spartan-3 FPGA 2.5V LVPECL and Low Voltage Differential Signaling (LVDS). Several interface modifications are presented with supporting IBIS simulation results.

This document details the design aspects of digital PLLs implemented in Virtex® and Spartan® FPGAs for telecommunications applications. PLL performance and loop stability are evaluated.

Design File(s):

• xapp868.zip

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet FFG1156

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet FF1156

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Virtex®-5 FF1759 Package

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet, for FFG1759 Virtex®-5 Package

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

This report describes the electrical performance characterization testing of the Virtex™-5 RocketIO™ GTP transceiver against the Fibre Channel specifications.

This report describes the electrical performance characterization testing of the Virtex™-5 RocketIO™ GTP transceiver against the Serial ATA Generation 2 (3 Gb/s) specification.

This report communicates the conditions, results, and procedural methods used to achieve a quantified test of interoperation between a Virtex™-5 GTP transceiver and a Virtex-4 RocketIO™ MGT.

This report communicates the conditions, results, and procedural methods used to achieve a quantified test of interoperation between a Virtex™-5 GTP transceiver and a Virtex-II Pro RocketIO™ MGT.

This characterization report compares the electrical performance of the Virtex®-5 FPGA RocketIO™ GTX transceiver against OIF-CEI-02.0, "Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps and 11G+ bps I/O".

This report compares the electrical performance of the Virtex®-5 FPGA RocketIO™ GTX transceiver against the 2.0 PCI Express® specifications.

This document serves as a general characterization report for the Virtex®-5 FPGA RocketIO™ GTX transceiver. The measurement results in this report provide a detailed view of the behavior of the transceiver across process, voltage, and temperature corners.

This characterization report compares the electrical performance of the Virtex®-5 FPGA RocketIO™ GTX transceiver against International Telecommunication Union Telecommunication Standardization Sector (ITU-T) Recommendation G.2851, The control of jitter and wander within the optical transport network (OTN).

This characterization report compares the electrical performance of the Virtex®-5 FPGA RocketIO™ GTX transceiver against the GR-253-CORE standard.

This characterization report provides FPGA characterization results for Virtex®-5 LXT and SXT RocketIO™ GTP transceivers across specified process, voltage, and temperature (PVT) conditions.

This report documents the results of characterization performed on the Virtex™-5 Clock Management Tile(CMT) that combines two enhanced Digital Clock Managers (DCMs) with one Phase-Locked Loop (PLL), and clocking resources.

This report describes the electrical performance characterization testing of the GTP transceiver against the Gigabit Ethernet serial protocol standards.

This report describes the electrical performance characterization testing of the GTP transceiver against the PCI Express specifications.

This report describes the electrical performance characterization testing of the GTP transceiver against the OC-48 specifications.

This report describes the electrical performance characterization testing of the Virtex®-5 FPGA RocketIO™ GTP transceiver against the 10 Gb Attachment Unit Interface (XAUI) specification.

This report describes the electrical performance characterization testing of the Virtex™-5 GTP transceiver against the Common Public Radio Interface (CPRI) specifications.

This white paper describes design techniques that improve signal integrity in Xilinx® FPGAs.

This white paper examines the industry's urgent need for higher rate interfaces (particularly 100 GbE), the important risks and concerns that a system architect has when adding 100 GbE to a platform, and several implementation options that show how FPGAs are uniquely positioned to handle these challenges.

This white paper examines alternate uses of available block RAM in Virtex® and Spartan® FPGAs.

This white paper explores solutions for implementing FIFOs in Virtex™-5 FPGAs.

This white paper examines how to remove the DC content from a digitally sampled waveform using DSP without complicated mathematics.

This white paper provides a high-level overview of RTCA DO-254 and EUROCAE ED-80 and discusses how Xilinx can assist designers of avionics systems to achieve certification.

This white paper explores the factors of PCI Express® technology and how they affect the performance of a system. This document also provides performance results from two systems that use the Xilinx® Endpoint Block Plus Wrapper for PCI Express in the Virtex®-5 FPGA Integrated Endpoint Block for PCI Express designs.

This white paper describes the steps necessary to analyze your design's power requirements using the Xilinx® Power Estimator.

This white paper defines IBIS models and describes how to use them to model I/O characteristics for Xilinx® FPGAs.

This white paper defines the use and limitations of bit error ratio measurements when analyzing the performance of communications links.

This white paper describes a rarely noticed design technique that can make a difference in the size and the performance of your FPGA design. Control signals on FPGA flip-flops have a built-in priority. If you can learn to write code that is sympathetic to the priorities, the results will be rewarding. This white paper provides some simple VHDL and Verilog examples to explain key points.

This white paper gives an overall view of the various mainstream digital television standards and outlines related Forward Error Correction solutions available from Xilinx for cable, satellite, terrestrial, and mobile systems.

This white paper discusses chip multiprocessing designs using the Xilinx Platform Studio

The innovative Virtex™-5 architecture, which is based on a real 6-input LUT with dual-LUT capability, provides substantial resource utilization advantages over competing architectures. This white paper details these advantages.

This white paper reviews the potential inaccuracies associated with the traditional one-resistor approach to selecting heatsinks, and suggests a more accurate two-resistor (2-R) approach based on both theta-jc and theta-jb from the device datasheet.

This paper focuses on how Xilinx Platform Flash PROMs simplify FPGA configuration design for system and board designers.

This white paper addresses power consumption in 65 nm FPGAs.

This white paper discusses the various memory interface controller design challenges and Xilinx solutions, including how to use the Xilinx software tools and hardware-verified reference designs to build a complete memory interface solution for your own application, from low-cost DDR SDRAM applications to higher-performance interfaces like the 667Mb/s DDR2 SDRAMs.

This document shows the level of performance that can be reached with Virtex™-5 family building blocks, with particular emphasis on the new ExpressFabric™ technology. The main features of this new technology, including the new 6-input LUT, are described.

When migrating or retargeting code from a previous design into a Virtex™-5 platform FPGA, some considerations should be addressed. This whitepaper identifies and details appropriate retargeting guidelines.

This white paper discusses some of the advantages made available to the application design engineer by the Virtex™-5 family’s advanced approach to FPGA packaging.

This white paper offers design tips on changes that can be made to the FPGA environment, features, and tool options to optimize the system design power consumption, thus reducing thermal and power component cost as well as increasing overall system reliability.

This white paper discusses signal analysis requirements and methods for printed circuit board design for Xilinx® FPGAs.

This white paper examines the causes of jitter, jitter measurement techniques, and methods of managing jitter in digital systems.

This white paper covers the different kinds of IIR filters and structures, and, with the use of The MathWorks® tools, shows how these structures can be mapped to the Xilinx® FPGA architecture.

The Virtex®-6 and Spartan®-6 architectures feature flexible internal memory resources that can be configured in a variety of different sizes. This white paper details the available features, illustrating the wide array of memory sizes available and shows the trade-off of using different resources to perform memory functions of different sizes.

This document explains the operation of the SPI-4.2 Dynamic Phase Alignment (DPA) Sink Core for Virtex®-4, Virtex-5, Virtex-6, and 7 series FPGAs and provides the guidelines on how to use the SPI-4.2 DPA solution.

This white paper addresses the flexible partial reconfiguration options when designing with 7 series, Virtex®-6, Virtex-5, and Virtex-4 FPGAs.

Modern CMOS processes with their smaller geometries cause certain undesirable side effects. These issues are reviewed with respect to their effect on system design using ASSP, ASIC, or FPGA devices, and what Xilinx has done to alleviate the potential problem.

This white paper updates the results from the 2005 Xilinx Rosetta experiments published in IEEE Transactions on Device and Materials Reliability, clarifies some open issues, and presents additional results for 90 nm and 65 nm technology nodes.

The ability to control system failure modes through fault-tolerant design requires an implementation methodology that ensures fault propagation can be controlled. Xilinx® Isolation Design Flow (IDF) provides fault containment at the FPGA module level, enabling single-chip fault tolerance by various techniques.

To communicate that Xilinx is discontinuing certain Development Systems Products.

This user guide provides a detailed description of each component and peripheral available on the ML501 Evaluation Platform. The ML501 board is a low-cost, entry-level platform for evaluation of Virtex®-5 LX FPGAs.

This guide describes the Virtex®-5 FPGA RocketIO™ Transceiver Signal Integrity Simulation (SIS) Kit for Synopsys HSPICE.

The ML505/ML506/ML507 Getting Started Tutorial provides step-by-step instructions for setting up and using the Virtex®-5 ML505, ML506, and ML507 Evaluation Platforms. These boards come with a number of pre-installed demonstrations. This tutorial guides you through these demonstrations and provides instructions to run them on the ML50x boards.

Design File(s):

• ML507 docs
• ML506 docs
• ML505 docs

This user guide introduces several designs that demonstrate Virtex®-5 device features using the ML505 (LXT), ML506 (SXT), and ML507 (FXT) Evaluation Platforms. The provided designs include processing systems based on the embedded PowerPC® 440 processor block, the MicroBlaze™ soft processor, the integrated Tri-mode Ethernet MAC, and the RocketIO™ GTP or GTX transceiver.

Design File(s):

• ML507 designs
• ML506 designs
• ML505 designs

This user guide describes the features and operation of the Virtex®-5 LXT, SXT, and FXT prototype platforms and describes how to configure chains of FPGAs and serial PROMs.

This tutorial provides step-by-step instructions for setting up and using the Virtex™-5 ML501 evaluation platform. The ML501 platform comes with a number of pre-installed demonstration and set-up programs. These programs are available on the System ACE interface, Platform Flash, and SPI Flash. This document guides designers through set-up and demonstration procedures.

Design File(s):

• Reference Designs

This user guide introduces several designs that demonstrate Virtex™-5 LX device features using the ML501 Evaluation Platform.

This user guide describes the Virtex®-5 FPGA ML550 Networking Interfaces board, which is the heart of the Virtex-5 FPGA ML550 Source-Synchronous Interfaces Tool Kit.

Design File(s):

• ug202.zip

The XGI SuperClock Module User Guide provides an overview of functionality, operation, and configuration of the SuperClock module add-on board.

This notice is to communicate that Xilinx is discontinuing certain Development Systems Products.

This user guide describes the Virtex™-5 FPGA ML555 Development Kit for PCI and PCI Express designs.

This signal integrity simulation kit provides a simulation environment for users to evaluate their channel designs with the Virtex®-5 FPGA RocketIO™ GTX transceivers. This document explains how to use the examples provided in the design kit and helps users modify them for their own needs.

This signal integrity simulation kit provides a simulation environment for users to evaluate their channel designs with the Virtex-5 FPGA RocketIO GTP transceivers. This document explains how to use the examples provided in the design kit and helps users modify them for their own needs.

This user guide describes the Virtex®-5 FPGA ML561 Memory Interfaces Development Board, which is the heart of the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit. The tool kit provides a complete development platform to interface with external memory devices for designing and verifying applications based on the Virtex-5 LXT Platform.

Design File(s):

• ML561 MIG Reference Design Files

This user guide describes the features and operation of the Virtex®-5 LXT and FXT FPGAs series of RocketIO™ characterization platforms, which includes the ML521, ML523, and ML525 boards.

This user guide showcases various features of the Virtex®-5 FXT FPGA ML507 development board. It describes the hardware platform, the HelloWorld software application, and the BlueCat Linux images.

Design File(s):

• ug511_mb_emb_ref.zip
• ug511_ppc440_emb_ref.zip

This user guide describes the features and operation of the Virtex®-5 LX FPGA prototype platform and provides instructions to configure chains of FPGAs and serial PROMs.

The ML50x boards enable designers to investigate and experiment with features of Virtex®-5 FPGAs. This user guide describes the features and operation of the ML505 (LXT), ML506 (SXT), and ML507 (FXT) Evaluation Platforms.

Design File(s):

• ML507 docs
• ML506 docs
• ML505 docs